Searched refs:fbdiv (Results 1 - 25 of 35) sorted by relevance

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/linux-master/drivers/clk/starfive/
H A Dclk-starfive-jh7110-pll.c15 * NI: integer frequency dividing ratio of feedback divider, set by fbdiv[11:0].
83 unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */ member in struct:jh7110_pll_preset
95 unsigned int fbdiv; member in struct:jh7110_pll_info::__anon200
102 u32 fbdiv; member in struct:jh7110_pll_info::__anon201
107 char fbdiv; member in struct:jh7110_pll_info::__anon202
118 .fbdiv = JH7110_PLL##_idx##_FBDIV_OFFSET, \
125 .fbdiv = JH7110_PLL##_idx##_FBDIV_MASK, \
130 .fbdiv = JH7110_PLL##_idx##_FBDIV_SHIFT, \
149 u32 fbdiv; member in struct:jh7110_pll_regvals
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/linux-master/drivers/clk/zynqmp/
H A Dpll.c104 u32 fbdiv; local
117 fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
118 if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) {
119 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
120 rate = *prate * fbdiv;
139 u32 fbdiv, data; local
145 ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv);
156 rate = parent_rate * fbdiv;
183 u32 fbdiv; local
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/linux-master/drivers/clk/zynq/
H A Dpll.c54 u32 fbdiv; local
56 fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
57 if (fbdiv < PLL_FBDIV_MIN)
58 fbdiv = PLL_FBDIV_MIN;
59 else if (fbdiv > PLL_FBDIV_MAX)
60 fbdiv = PLL_FBDIV_MAX;
62 return *prate * fbdiv;
75 u32 fbdiv; local
78 * makes probably sense to redundantly save fbdiv in the struct
81 fbdiv
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/linux-master/drivers/clk/analogbits/
H A Dwrpll-cln28hpc.c232 u8 fbdiv, divq, best_r, r; local
268 fbdiv = __wrpll_calc_fbdiv(c);
280 f >>= (fbdiv - 1);
283 vco_pre = fbdiv * post_divr_freq;
339 u8 fbdiv; local
347 fbdiv = __wrpll_calc_fbdiv(c);
348 n = parent_rate * fbdiv * (c->divf + 1);
/linux-master/drivers/clk/mmp/
H A Dclk-pll.c49 u32 fbdiv, refdiv, postdiv; local
59 fbdiv = (val >> pll->shift) & 0x1ff;
62 fbdiv = 2;
74 rate *= 2 * fbdiv;
88 rate *= fbdiv + 2;
/linux-master/drivers/clk/berlin/
H A Dberlin2-pll.c39 * clkout = fbdiv / refdiv * parent / vcodiv
46 u32 val, fbdiv, rfdiv, vcodivsel, vcodiv; local
50 fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK;
66 rate *= fbdiv * map->mult;
H A Dberlin2-avpll.c159 u32 reg, refdiv, fbdiv; local
162 /* AVPLL VCO frequency: Fvco = (Fref / refdiv) * fbdiv */
166 fbdiv = (reg & VCO_FBDIV_MASK) >> VCO_FBDIV_SHIFT;
167 freq *= fbdiv;
/linux-master/drivers/clk/axs10x/
H A Di2s_pll_clock.c27 unsigned int fbdiv; member in struct:i2s_pll_cfg
102 unsigned int idiv, fbdiv, odiv; local
105 fbdiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_FBDIV_REG));
108 return ((parent_rate / idiv) * fbdiv) / odiv;
145 i2s_pll_write(clk, PLL_FBDIV_REG, pll_cfg[i].fbdiv);
H A Dpll_clock.c69 u32 fbdiv; member in struct:axs10x_pll_cfg
139 u32 idiv, fbdiv, odiv; local
143 fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV));
146 rate = (u64)parent_rate * fbdiv;
185 axs10x_encode_div(pll_cfg[i].fbdiv, 0));
/linux-master/drivers/clk/pistachio/
H A Dclk-pll.c211 vco *= (params->fbdiv << 24) + params->frac;
230 (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT);
273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; local
277 fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK;
289 rate *= (fbdiv << 24) + frac;
291 rate *= (fbdiv << 24);
366 vco = div_u64(params->fref * params->fbdiv, params->refdiv);
398 (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT) |
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; local
418 fbdiv
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H A Dclk.h98 unsigned long long fbdiv; member in struct:pistachio_pll_rate_table
/linux-master/drivers/clk/
H A Dclk-hsdk-pll.c49 u32 fbdiv; member in struct:hsdk_pll_cfg
142 val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
172 u32 idiv, fbdiv, odiv; local
189 /* fb divider = 2*(reg.fbdiv + 1) */
190 fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
194 rate = (u64)parent_rate * fbdiv;
H A Dclk-sp7021.c405 u32 fbdiv; local
408 fbdiv = DIV_ROUND_CLOSEST(rate, clk->brate);
409 if (fbdiv > max)
410 fbdiv = max;
412 return fbdiv;
473 u32 fbdiv = ((reg >> clk->div_shift) & ((1 << clk->div_width) - 1)) + 1; local
475 ret = clk->brate * fbdiv;
497 u32 fbdiv = sp_pll_calc_div(clk, rate); local
501 reg |= ((fbdiv - 1) << clk->div_shift) & mask;
H A Dclk-axm5516.c52 unsigned long rate, fbdiv, refdiv, postdiv; local
57 fbdiv = ((control >> 4) & 0xfff) + 3;
59 rate = (parent_rate / (refdiv * postdiv)) * fbdiv;
H A Dclk-bm1880.c477 u32 fbdiv, refdiv; local
480 fbdiv = (regval >> 16) & 0xfff;
485 numerator = parent_rate * fbdiv;
/linux-master/drivers/clk/rockchip/
H A Dclk-pll.c145 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT)
172 rate64 *= cur.fbdiv;
200 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
201 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
214 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
317 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
318 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
320 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
321 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
324 if (rate->fbdiv !
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/linux-master/drivers/gpu/drm/radeon/
H A Drv740_dpm.c132 u32 fbdiv; local
144 fbdiv = (u32) tmp;
154 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
164 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
H A Drv730_dpm.c51 u32 fbdiv; local
69 fbdiv = (u32) tmp;
85 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
95 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);
H A Drs780_dpm.c212 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; local
214 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
217 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
/linux-master/drivers/phy/rockchip/
H A Dphy-rockchip-inno-hdmi.c254 u16 fbdiv; member in struct:pre_pll_config
269 u16 fbdiv; member in struct:post_pll_config
797 RK3228_PRE_PLL_FB_DIV_8(cfg->fbdiv) |
800 inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
958 inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val);
959 inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
1073 RK3228_POST_PLL_FB_DIV_8(cfg->fbdiv));
1074 inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
1181 inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
1183 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
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H A Dphy-rockchip-inno-dsidphy.c221 u16 fbdiv; member in struct:inno_dsidphy::__anon40
359 inno->pll.fbdiv = best_fbdiv;
387 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));
389 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
530 u16 fbdiv = 28; local
545 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv));
547 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv));
/linux-master/sound/soc/codecs/
H A Dmadera.c4423 int refdiv, fref, fout, lockdet_thr, fbdiv, hp, fast_clk, fllgcd; local
4447 fbdiv = 256;
4449 fbdiv = 4;
4453 fbdiv = 1;
4457 fbdiv = 1;
4482 while (ratio / fbdiv < min_n) {
4483 fbdiv /= 2;
4484 if (fbdiv < 1) {
4485 madera_fll_err(fll, "FBDIV (%d) must be >= 1\n", fbdiv);
4489 while (frac && (ratio / fbdiv > max_
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/linux-master/drivers/clk/ralink/
H A Dclk-mt7621.c262 u32 pll, prediv, fbdiv; local
278 fbdiv = FIELD_GET(CPU_PLL_FBDIV_MASK, pll);
280 cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
/linux-master/drivers/clk/xilinx/
H A Dxlnx_vcu.c82 * @fbdiv: The integer portion of the feedback divider to the PLL
90 u32 fbdiv; member in struct:xvcu_pll_cfg
279 if (xvcu_pll_cfg[i].fbdiv == div)
298 vcu_pll_ctrl |= FIELD_PREP(VCU_PLL_CTRL_FBDIV, cfg->fbdiv);
/linux-master/arch/arm/common/
H A Dsa1111.c1180 unsigned int skcdr, fbdiv, ipdiv, opdiv; local
1184 fbdiv = (skcdr & 0x007f) + 2;
1188 return 3686400 * fbdiv / (ipdiv * opdiv);

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