Searched refs:engine_id (Results 1 - 25 of 108) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/bios/
H A Dcommand_table_helper_struct.h40 bool (*engine_bp_to_atom)(enum engine_id engine_id,
57 uint8_t (*dig_encoder_sel_to_atom)(enum engine_id engine_id);
/linux-master/drivers/gpu/drm/nouveau/nvkm/falcon/
H A Dga100.c38 FLCN_DBG(falcon, "brom: %08x %08x", fw->engine_id, fw->ucode_id);
41 if (fw->engine_id & 0x00000001) {
44 if (fw->engine_id & 0x00000004) {
47 if (fw->engine_id & 0x00000400) {
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_arcturus.h26 uint32_t engine_id, uint32_t queue_id,
H A Damdgpu_amdkfd_arcturus.c69 unsigned int engine_id,
75 switch (engine_id) {
79 engine_id);
118 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
194 uint32_t engine_id, uint32_t queue_id,
198 engine_id, queue_id);
68 get_sdma_rlc_reg_offset(struct amdgpu_device *adev, unsigned int engine_id, unsigned int queue_id) argument
193 kgd_arcturus_hqd_sdma_dump(struct amdgpu_device *adev, uint32_t engine_id, uint32_t queue_id, uint32_t (**dump)[2], uint32_t *n_regs) argument
H A Damdgpu_amdkfd_gc_9_4_3.c44 unsigned int engine_id,
48 SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id),
54 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
129 uint32_t engine_id, uint32_t queue_id,
133 engine_id, queue_id);
43 get_sdma_rlc_reg_offset(struct amdgpu_device *adev, unsigned int engine_id, unsigned int queue_id) argument
128 kgd_gfx_v9_4_3_hqd_sdma_dump(struct amdgpu_device *adev, uint32_t engine_id, uint32_t queue_id, uint32_t (**dump)[2], uint32_t *n_regs) argument
H A Damdgpu_amdkfd_gfx_v10_3.c130 unsigned int engine_id,
136 switch (engine_id) {
140 engine_id);
163 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
429 uint32_t engine_id, uint32_t queue_id,
433 engine_id, queue_id);
129 get_sdma_rlc_reg_offset(struct amdgpu_device *adev, unsigned int engine_id, unsigned int queue_id) argument
428 hqd_sdma_dump_v10_3(struct amdgpu_device *adev, uint32_t engine_id, uint32_t queue_id, uint32_t (**dump)[2], uint32_t *n_regs) argument
/linux-master/drivers/gpu/drm/amd/display/dc/inc/
H A Dlink_enc_cfg.h84 enum engine_id eng_id);
89 enum engine_id eng_id);
113 bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct dc_link *link);
/linux-master/drivers/gpu/drm/amd/display/include/
H A Dbios_parser_types.h113 enum engine_id engine_id; member in struct:bp_encoder_control
124 enum engine_id engine_id; member in struct:bp_external_encoder_control
136 enum engine_id engine_id; member in struct:bp_crtc_source_select
148 enum engine_id engine_id; member in struct:bp_transmitter_control
156 enum engine_id hpo_engine_id; /* used for DCN3 */
H A Daudio_types.h106 enum engine_id engine_id; member in struct:audio_output
H A Dgrph_object_id.h177 enum engine_id { enum
295 static inline enum engine_id dal_graphics_object_id_get_engine_id(
299 return (enum engine_id) id.id;
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_i2c_hw.c334 DC_I2C_DDC_SELECT, dce_i2c_hw->engine_id);
623 uint32_t engine_id,
629 dce_i2c_hw->engine_id = engine_id;
646 uint32_t engine_id,
653 engine_id,
663 uint32_t engine_id,
670 engine_id,
680 uint32_t engine_id,
687 engine_id,
620 dce_i2c_hw_construct( struct dce_i2c_hw *dce_i2c_hw, struct dc_context *ctx, uint32_t engine_id, const struct dce_i2c_registers *regs, const struct dce_i2c_shift *shifts, const struct dce_i2c_mask *masks) argument
643 dce100_i2c_hw_construct( struct dce_i2c_hw *dce_i2c_hw, struct dc_context *ctx, uint32_t engine_id, const struct dce_i2c_registers *regs, const struct dce_i2c_shift *shifts, const struct dce_i2c_mask *masks) argument
660 dce112_i2c_hw_construct( struct dce_i2c_hw *dce_i2c_hw, struct dc_context *ctx, uint32_t engine_id, const struct dce_i2c_registers *regs, const struct dce_i2c_shift *shifts, const struct dce_i2c_mask *masks) argument
677 dcn1_i2c_hw_construct( struct dce_i2c_hw *dce_i2c_hw, struct dc_context *ctx, uint32_t engine_id, const struct dce_i2c_registers *regs, const struct dce_i2c_shift *shifts, const struct dce_i2c_mask *masks) argument
694 dcn2_i2c_hw_construct( struct dce_i2c_hw *dce_i2c_hw, struct dc_context *ctx, uint32_t engine_id, const struct dce_i2c_registers *regs, const struct dce_i2c_shift *shifts, const struct dce_i2c_mask *masks) argument
[all...]
H A Ddce_i2c_hw.h290 uint32_t engine_id; member in struct:dce_i2c_hw
304 uint32_t engine_id,
312 uint32_t engine_id,
320 uint32_t engine_id,
328 uint32_t engine_id,
336 uint32_t engine_id,
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/
H A Dga102.c84 fw->engine_id = meta[1];
103 FLCN_DBG(falcon, "brom: %08x %08x", fw->engine_id, fw->ucode_id);
106 if (fw->engine_id & 0x00000400) {
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dlink_encoder.h85 enum engine_id preferred_engine;
144 enum engine_id engine,
184 enum engine_id eng_id;
231 enum engine_id preferred_engine;
/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_link_enc_cfg.c82 enum engine_id eng_id)
102 enum engine_id eng_id)
137 enum engine_id eng_id)
170 static enum engine_id find_first_avail_link_enc(
173 enum engine_id eng_id_requested)
175 enum engine_id eng_id = ENGINE_ID_UNKNOWN;
199 static bool is_avail_link_enc(struct dc_state *state, enum engine_id eng_id, struct dc_stream_state *stream)
274 state->res_ctx.link_enc_cfg_ctx.link_enc_avail[i] = (enum engine_id) i;
302 enum engine_id eng_id = ENGINE_ID_UNKNOWN, eng_id_req = ENGINE_ID_UNKNOWN;
450 enum engine_id eng_i
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/bios/dce80/
H A Dcommand_table_helper_dce80.c61 static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
239 static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
/linux-master/drivers/gpu/drm/amd/display/dc/bios/dce112/
H A Dcommand_table_helper_dce112.c151 static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
212 static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
H A Dcommand_table_helper2_dce112.c151 static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
212 static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
/linux-master/drivers/gpu/drm/amd/display/dc/bios/dce110/
H A Dcommand_table_helper_dce110.c154 static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
210 static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
/linux-master/drivers/gpu/drm/amd/display/dc/bios/dce60/
H A Dcommand_table_helper_dce60.c61 static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
239 static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
/linux-master/drivers/gpu/drm/amd/display/dc/virtual/
H A Dvirtual_link_encoder.c77 enum engine_id engine,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dio_stream_encoder.c74 cntl.engine_id = enc1->base.id;
115 cntl.engine_id = enc1->base.id;
509 enum engine_id eng_id,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dio_stream_encoder.c107 cntl.engine_id = enc1->base.id;
148 cntl.engine_id = enc1->base.id;
478 enum engine_id eng_id,
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/acr/
H A Dga102.c108 .engine_id = lsfw->engine_id,
119 hdr->hs_fmc_params.engid_mask = lsfw->engine_id;
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dio_stream_encoder.c63 cntl.engine_id = enc1->base.id;
103 cntl.engine_id = enc1->base.id;
508 enum engine_id eng_id,

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