/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
H A D | dcn35_dpp.c | 31 #define REG(reg) dpp->tf_regs->reg 33 #define CTX dpp->base.ctx 37 ((const struct dcn35_dpp_shift *)(dpp->tf_shift))->field_name, \ 38 ((const struct dcn35_dpp_mask *)(dpp->tf_mask))->field_name 40 bool dpp35_construct(struct dcn3_dpp *dpp, struct dc_context *ctx, argument 45 return dpp32_construct(dpp, ctx, inst, tf_regs, 50 void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable) argument
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H A D | dcn35_dpp.h | 55 void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable);
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
H A D | dpp.h | 69 struct dpp { struct 198 struct dpp *dpp_base, const struct pwl_params *params); 200 void (*dpp_set_pre_degam)(struct dpp *dpp_base, 203 void (*dpp_program_cm_dealpha)(struct dpp *dpp_base, 207 struct dpp *dpp_base, 210 void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s); 212 void (*dpp_reset)(struct dpp *dpp); 214 void (*dpp_set_scaler)(struct dpp *dp [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/ |
H A D | dcn30_dpp_cm.c | 34 dpp->tf_regs->reg 37 dpp->base.ctx 41 dpp->tf_shift->field_name, dpp->tf_mask->field_name 44 struct dpp *dpp_base) 46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 57 static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base) 62 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 78 struct dpp *dpp_base, 84 struct dcn3_dpp *dpp local 130 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 149 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 160 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 168 dpp3_gamcor_reg_field( struct dcn3_dpp *dpp, struct dcn3_xfer_func_reg *reg) argument 205 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 220 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 308 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 314 program_gamut_remap( struct dcn3_dpp *dpp, const uint16_t *regval, int select) argument 377 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 409 read_gamut_remap(struct dcn3_dpp *dpp, uint16_t *regval, int *select) argument 447 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local [all...] |
H A D | dcn30_dpp.c | 34 dpp->tf_regs->reg 37 dpp->base.ctx 41 dpp->tf_shift->field_name, dpp->tf_mask->field_name 44 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) 46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 86 /*program post scaler scs block in dpp CM*/ 88 struct dpp *dpp_base, 93 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 133 gam_regs.shifts.csc_c11 = dpp 163 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 211 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 389 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 418 dpp3_get_optimal_number_of_taps( struct dpp *dpp, struct scaler_data *scl_data, const struct scaling_taps *in_taps) argument 522 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 570 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 590 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 607 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 624 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 639 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 669 dcn3_dpp_cm_get_reg_field( struct dcn3_dpp *dpp, struct dcn3_xfer_func_reg *reg) argument 701 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 729 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 758 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 788 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 831 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 858 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 884 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 900 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 1050 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 1202 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 1244 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 1291 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 1310 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 1326 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 1360 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 1379 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); local 1507 dpp3_construct( struct dcn3_dpp *dpp, struct dc_context *ctx, uint32_t inst, const struct dcn3_dpp_registers *tf_regs, const struct dcn3_dpp_shift *tf_shift, const struct dcn3_dpp_mask *tf_mask) argument [all...] |
H A D | dcn30_dpp.h | 30 #define TO_DCN30_DPP(dpp)\ 31 container_of(dpp, struct dcn3_dpp, base) 559 struct dpp base; 585 struct dpp *dpp_base, const struct pwl_params *params); 588 struct dpp *dpp_base, 591 void dpp30_read_state(struct dpp *dpp_base, 595 struct dpp *dpp, 600 struct dpp *dpp_base, 608 struct dpp *dpp_bas [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
H A D | dcn10_dpp_cm.c | 43 dpp->tf_regs->reg 46 dpp->base.ctx 50 dpp->tf_shift->field_name, dpp->tf_mask->field_name 92 struct dcn10_dpp *dpp, 118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; 119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; 120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; 121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; 129 dpp 91 program_gamut_remap( struct dcn10_dpp *dpp, const uint16_t *regval, enum gamut_remap_select select) argument 164 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 184 read_gamut_remap(struct dcn10_dpp *dpp, uint16_t *regval, enum gamut_remap_select *select) argument 236 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 252 dpp1_cm_program_color_matrix( struct dcn10_dpp *dpp, const uint16_t *regval) argument 311 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 324 dpp1_cm_get_reg_field( struct dcn10_dpp *dpp, struct xfer_func_reg *reg) argument 351 dpp1_cm_get_degamma_reg_field( struct dcn10_dpp *dpp, struct xfer_func_reg *reg) argument 381 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 389 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 401 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 422 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 436 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 465 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 494 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 568 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 589 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 618 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 645 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 655 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 665 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 695 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 710 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 733 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 775 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 802 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 833 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 881 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local [all...] |
H A D | dcn10_dpp.c | 42 dpp->tf_regs->reg 45 dpp->base.ctx 49 dpp->tf_shift->field_name, dpp->tf_mask->field_name 94 void dpp_read_state(struct dpp *dpp_base, 97 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 125 struct dpp *dpp, 131 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && 137 dpp 124 dpp1_get_optimal_number_of_taps( struct dpp *dpp, struct scaler_data *scl_data, const struct scaling_taps *in_taps) argument 190 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 206 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 263 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 288 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 415 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 438 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 493 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 506 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 559 dpp1_construct( struct dcn10_dpp *dpp, struct dc_context *ctx, uint32_t inst, const struct dcn_dpp_registers *tf_regs, const struct dcn_dpp_shift *tf_shift, const struct dcn_dpp_mask *tf_mask) argument [all...] |
H A D | dcn10_dpp_dscl.c | 44 dpp->tf_regs->reg 47 dpp->base.ctx 51 dpp->tf_shift->field_name, dpp->tf_mask->field_name 124 struct dpp *dpp_base, 158 struct dpp *dpp_base, 161 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local 163 if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) { 168 if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) { 169 dpp 179 dpp1_dscl_set_lb( struct dcn10_dpp *dpp, const struct line_buffer_params *lb_params, enum lb_memory_config mem_size_config) argument 240 dpp1_dscl_set_scaler_filter( struct dcn10_dpp *dpp, uint32_t taps, enum dcn10_coef_filter_type_sel filter_type, const uint16_t *filter) argument 278 dpp1_dscl_set_scl_filter( struct dcn10_dpp *dpp, const struct scaler_data *scl_data, bool chroma_coef_mode) argument 459 dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp, const struct scaler_data *scl_data) argument 510 dpp1_dscl_set_manual_ratio_init( struct dcn10_dpp *dpp, const struct scaler_data *data) argument 587 dpp1_dscl_set_recout(struct dcn10_dpp *dpp, const struct rect *recout) argument 617 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); local [all...] |
H A D | dcn10_dpp.h | 28 #include "dpp.h" 30 #define TO_DCN10_DPP(dpp)\ 31 container_of(dpp, struct dcn10_dpp, base) 1357 struct dpp base; 1382 struct dpp *dpp_base, 1386 struct dpp *dpp_base, 1393 struct dpp *dpp_base, 1408 struct dpp *dpp_base, 1412 struct dpp *dpp_base, 1416 struct dpp *dpp_bas [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/ |
H A D | dcn201_dpp.c | 35 dpp->tf_regs->reg 38 dpp->base.ctx 42 dpp->tf_shift->field_name, dpp->tf_mask->field_name 45 struct dpp *dpp_base, 52 struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base); local 184 struct dpp *dpp, 190 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && 195 dpp 183 dpp201_get_optimal_number_of_taps( struct dpp *dpp, struct scaler_data *scl_data, const struct scaling_taps *in_taps) argument 286 dpp201_construct( struct dcn201_dpp *dpp, struct dc_context *ctx, uint32_t inst, const struct dcn201_dpp_registers *tf_regs, const struct dcn201_dpp_shift *tf_shift, const struct dcn201_dpp_mask *tf_mask) argument [all...] |
H A D | dcn201_dpp.h | 30 #define TO_DCN201_DPP(dpp)\ 31 container_of(dpp, struct dcn201_dpp, base) 58 struct dpp base;
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/ |
H A D | dcn20_dpp.c | 42 dpp->tf_regs->reg 45 dpp->base.ctx 49 dpp->tf_shift->field_name, dpp->tf_mask->field_name 51 void dpp20_read_state(struct dpp *dpp_base, 54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 78 struct dpp *dpp_base, 81 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 93 struct dpp *dpp_base, 98 struct dpp *dpp_bas 105 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 320 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 344 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 368 oppn20_dummy_program_regamma_pwl( struct dpp *dpp, const struct pwl_params *params, enum opp_regamma mode) argument 406 dpp2_construct( struct dcn20_dpp *dpp, struct dc_context *ctx, uint32_t inst, const struct dcn2_dpp_registers *tf_regs, const struct dcn2_dpp_shift *tf_shift, const struct dcn2_dpp_mask *tf_mask) argument [all...] |
H A D | dcn20_dpp_cm.c | 37 dpp->tf_regs->reg 43 dpp->base.ctx 47 dpp->tf_shift->field_name, dpp->tf_mask->field_name 51 struct dpp *dpp_base) 53 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 65 struct dpp *dpp_base, 70 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 86 struct dpp *dpp_base, 93 struct dcn20_dpp *dpp local 138 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 161 program_gamut_remap( struct dcn20_dpp *dpp, const uint16_t *regval, enum dcn20_gamut_remap_select select) argument 217 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 237 read_gamut_remap(struct dcn20_dpp *dpp, uint16_t *regval, enum dcn20_gamut_remap_select *select) argument 276 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 298 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 369 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 380 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 395 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 413 dcn20_dpp_cm_get_reg_field( struct dcn20_dpp *dpp, struct xfer_func_reg *reg) argument 445 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 473 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 500 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 527 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 566 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 593 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 619 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 635 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 785 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 938 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 974 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 1020 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 1039 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 1055 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 1089 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 1108 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local 1199 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
H A D | dcn32_dpp.c | 147 struct dcn3_dpp *dpp, 154 dpp->base.ctx = ctx; 156 dpp->base.inst = inst; 157 dpp->base.funcs = &dcn32_dpp_funcs; 158 dpp->base.caps = &dcn32_dpp_cap; 160 dpp->tf_regs = tf_regs; 161 dpp->tf_shift = tf_shift; 162 dpp->tf_mask = tf_mask; 146 dpp32_construct( struct dcn3_dpp *dpp, struct dc_context *ctx, uint32_t inst, const struct dcn3_dpp_registers *tf_regs, const struct dcn3_dpp_shift *tf_shift, const struct dcn3_dpp_mask *tf_mask) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
H A D | dcn201_resource.c | 620 static void dcn201_dpp_destroy(struct dpp **dpp) argument 622 kfree(TO_DCN201_DPP(*dpp)); 623 *dpp = NULL; 626 static struct dpp *dcn201_dpp_create( 630 struct dcn201_dpp *dpp = local 633 if (!dpp) 636 if (dpp201_construct(dpp, ctx, inst, 638 return &dpp->base; 640 kfree(dpp); [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
H A D | dcn10_hwseq.c | 299 struct dpp *dpp = pool->dpps[i]; local 302 dpp->funcs->dpp_read_state(dpp, &s); 303 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap); 313 dpp->inst, 354 dc->caps.color.dpp.input_lut_shared, 355 dc->caps.color.dpp.icsc, 356 dc->caps.color.dpp 1282 dcn10_plane_atomic_power_down(struct dc *dc, struct dpp *dpp, struct hubp *hubp) argument 1318 struct dpp *dpp = pipe_ctx->plane_res.dpp; local 1433 struct dpp *dpp = dc->res_pool->dpps[i]; local 1891 struct dpp *dpp = pipe_ctx->plane_res.dpp; local 2640 dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state) argument 2767 struct dpp *dpp = pipe_ctx->plane_res.dpp; local 3473 struct dpp *dpp = pipe_ctx->plane_res.dpp; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
H A D | dcn10_resource.c | 574 static void dcn10_dpp_destroy(struct dpp **dpp) argument 576 kfree(TO_DCN10_DPP(*dpp)); 577 *dpp = NULL; 580 static struct dpp *dcn10_dpp_create( 584 struct dcn10_dpp *dpp = local 587 if (!dpp) 590 dpp1_construct(dpp, ctx, inst, 592 return &dpp->base; 1115 idle_pipe->plane_res.dpp [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
H A D | dcn30_hwseq.c | 87 struct dpp *dpp = pool->dpps[i]; local 90 dpp->funcs->dpp_read_state(dpp, &s); 91 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap); 101 dpp->inst, 147 dc->caps.color.dpp.input_lut_shared, 148 dc->caps.color.dpp.icsc, 149 dc->caps.color.dpp [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
H A D | dcn201_hwseq.c | 285 struct dpp *dpp = res_pool->dpps[i]; local 287 dpp->funcs->dpp_reset(dpp); 305 struct dpp *dpp = res_pool->dpps[i]; local 311 pipe_ctx->plane_res.dpp = dpp; 312 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 313 hubp->mpcc_id = dpp [all...] |
/linux-master/arch/sparc/vdso/ |
H A D | vma.c | 250 struct page *dp, **dpp = NULL; local 290 dpp = kcalloc(dnpages, sizeof(struct page *), GFP_KERNEL); 291 vvar_mapping.pages = dpp; 293 if (!dpp) 300 dpp[0] = dp; 318 if (dpp != NULL) { 320 if (dpp[i] != NULL) 321 __free_page(dpp[i]); 323 kfree(dpp);
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
H A D | dcn302_resource.c | 538 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) 540 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); local 542 if (!dpp) 545 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 546 return &dpp->base; 549 kfree(dpp); 1239 dc->caps.color.dpp.dcn_arch = 1; 1240 dc->caps.color.dpp.input_lut_shared = 0; 1241 dc->caps.color.dpp.icsc = 1; 1242 dc->caps.color.dpp [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
H A D | dcn303_resource.c | 516 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) 518 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); local 520 if (!dpp) 523 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 524 return &dpp->base; 527 kfree(dpp); 1181 dc->caps.color.dpp.dcn_arch = 1; 1182 dc->caps.color.dpp.input_lut_shared = 0; 1183 dc->caps.color.dpp.icsc = 1; 1184 dc->caps.color.dpp [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
H A D | dcn20_resource.h | 80 void dcn20_dpp_destroy(struct dpp **dpp); 82 struct dpp *dcn20_dpp_create(
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/ |
H A D | hw_sequencer_private.h | 66 struct dpp; 114 struct dpp *dpp,
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