1/* Copyright 2016 Advanced Micro Devices, Inc.
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * Authors: AMD
22 *
23 */
24
25#ifndef __DCN201_DPP_H__
26#define __DCN201_DPP_H__
27
28#include "dcn20/dcn20_dpp.h"
29
30#define TO_DCN201_DPP(dpp)\
31	container_of(dpp, struct dcn201_dpp, base)
32
33#define TF_REG_LIST_DCN201(id) \
34	TF_REG_LIST_DCN20(id)
35
36#define TF_REG_LIST_SH_MASK_DCN201(mask_sh)\
37	TF_REG_LIST_SH_MASK_DCN20(mask_sh)
38
39#define TF_REG_FIELD_LIST_DCN201(type) \
40	TF_REG_FIELD_LIST_DCN2_0(type)
41
42struct dcn201_dpp_shift {
43	TF_REG_FIELD_LIST_DCN201(uint8_t);
44};
45
46struct dcn201_dpp_mask {
47	TF_REG_FIELD_LIST_DCN201(uint32_t);
48};
49
50#define DPP_DCN201_REG_VARIABLE_LIST \
51	DPP_DCN2_REG_VARIABLE_LIST
52
53struct dcn201_dpp_registers {
54	DPP_DCN201_REG_VARIABLE_LIST;
55};
56
57struct dcn201_dpp {
58	struct dpp base;
59
60	const struct dcn201_dpp_registers *tf_regs;
61	const struct dcn201_dpp_shift *tf_shift;
62	const struct dcn201_dpp_mask *tf_mask;
63
64	const uint16_t *filter_v;
65	const uint16_t *filter_h;
66	const uint16_t *filter_v_c;
67	const uint16_t *filter_h_c;
68	int lb_pixel_depth_supported;
69	int lb_memory_size;
70	int lb_bits_per_entry;
71	bool is_write_to_ram_a_safe;
72	struct scaler_data scl_data;
73	struct pwl_params pwl_data;
74};
75
76bool dpp201_construct(struct dcn201_dpp *dpp2,
77	struct dc_context *ctx,
78	uint32_t inst,
79	const struct dcn201_dpp_registers *tf_regs,
80	const struct dcn201_dpp_shift *tf_shift,
81	const struct dcn201_dpp_mask *tf_mask);
82
83#endif /* __DC_HWSS_DCN201_H__ */
84