Searched refs:dpm (Results 1 - 25 of 38) sorted by relevance

12

/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dlegacy_dpm.c127 if (rps == adev->pm.dpm.current_ps)
129 if (rps == adev->pm.dpm.requested_ps)
131 if (rps == adev->pm.dpm.boot_ps)
143 for (i = 0; i < adev->pm.dpm.num_ps; i++)
144 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
172 adev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
173 adev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
174 adev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
242 adev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst;
243 adev->pm.dpm
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H A DMakefile23 AMD_LEGACYDPM_PATH = ../pm/legacy-dpm
H A Dkv_dpm.c77 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
99 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
367 struct kv_power_info *pi = adev->pm.dpm.priv;
791 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
893 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
966 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1027 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1093 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1152 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1219 adev->pm.dpm
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H A Dsi_dpm.c1854 struct si_power_info *pi = adev->pm.dpm.priv;
1927 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1928 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1956 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1963 struct ni_power_info *pi = adev->pm.dpm.priv;
2217 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2220 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2223 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2224 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm
[all...]
/linux-master/drivers/gpu/drm/radeon/
H A Dr600_dpm.c145 if (rps == rdev->pm.dpm.current_ps)
147 if (rps == rdev->pm.dpm.requested_ps)
149 if (rps == rdev->pm.dpm.boot_ps)
756 rdev->pm.dpm.thermal.min_temp = low_temp;
757 rdev->pm.dpm.thermal.max_temp = high_temp;
856 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
857 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
858 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
893 rdev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst;
894 rdev->pm.dpm
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H A Dradeon_pm.c79 rdev->pm.dpm.ac_power = true;
81 rdev->pm.dpm.ac_power = false;
83 if (rdev->asic->dpm.enable_bapm)
84 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
418 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
436 /* we don't support the legacy modes with dpm */
471 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
488 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
490 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
492 rdev->pm.dpm
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H A Dci_dpm.c169 struct ci_power_info *pi = rdev->pm.dpm.priv;
254 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
256 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
258 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
259 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
262 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
263 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
264 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
265 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
266 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm
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H A Drs780_dpm.c44 struct igp_power_info *pi = rdev->pm.dpm.priv;
380 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
407 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
600 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
652 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
653 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
742 rdev->pm.dpm.boot_ps = rps;
744 rdev->pm.dpm.uvd_ps = rps;
807 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,
810 if (!rdev->pm.dpm
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H A Dbtc_dpm.c1201 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values,
1208 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values,
1251 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio)
1255 (rdev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
1256 rdev->pm.dpm.dyn_state.mclk_sclk_ratio);
1258 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta)
1262 rdev->pm.dpm.dyn_state.sclk_mclk_delta);
1289 if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) {
1291 (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta));
1295 if ((*vddci - *vddc) > rdev->pm.dpm
[all...]
H A Drv770_dpm.c58 struct rv7xx_power_info *pi = rdev->pm.dpm.priv;
65 struct evergreen_power_info *pi = rdev->pm.dpm.priv;
1192 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) {
1195 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT)
1198 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT)
1202 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1348 if (rdev->pm.dpm.new_active_crtcs & 1) {
1351 } else if (rdev->pm.dpm.new_active_crtcs & 2) {
1500 rdev->pm.dpm.forced_level = level;
1709 voltage_response_time = (u32)rdev->pm.dpm
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H A Drv6xx_dpm.c45 struct rv6xx_power_info *pi = rdev->pm.dpm.priv;
921 rdev->pm.dpm.voltage_response_time,
925 rdev->pm.dpm.backbias_response_time,
1185 if (rdev->pm.dpm.new_active_crtcs & 1) {
1188 } else if (rdev->pm.dpm.new_active_crtcs & 2) {
1298 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);
1548 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1553 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1615 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1633 if (rdev->pm.dpm
[all...]
H A Dsi_dpm.c1701 struct si_power_info *pi = rdev->pm.dpm.priv;
1775 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1776 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
2066 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2069 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2072 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2073 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2075 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2076 adjustment_delta = rdev->pm.dpm
[all...]
H A Dni_dpm.c728 struct ni_power_info *pi = rdev->pm.dpm.priv;
795 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
801 if (rdev->pm.dpm.ac_power)
802 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
804 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
806 if (rdev->pm.dpm.ac_power == false) {
873 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
876 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
879 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
882 btc_apply_voltage_dependency_rules(&rdev->pm.dpm
[all...]
H A Dkv_dpm.c152 struct kv_power_info *pi = rdev->pm.dpm.priv;
398 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
420 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
561 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
663 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
736 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
797 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
863 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
922 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1120 kv_update_current_ps(rdev, rdev->pm.dpm
[all...]
H A Dtrinity_dpm.c309 struct trinity_power_info *pi = rdev->pm.dpm.priv;
1013 rdev->pm.dpm.thermal.min_temp = low_temp;
1014 rdev->pm.dpm.thermal.max_temp = high_temp;
1076 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1124 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1179 rdev->pm.dpm.forced_level = level;
1187 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1208 trinity_dpm_bapm_enable(rdev, rdev->pm.dpm.ac_power);
1462 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1499 u32 num_active_displays = rdev->pm.dpm
[all...]
H A Dcypress_dpm.c1638 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1641 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1644 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1751 if (rdev->pm.dpm.new_active_crtc_count > 0)
1756 if (rdev->pm.dpm.new_active_crtc_count > 1)
1766 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
1767 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
1770 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
1783 cypress_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
1810 struct radeon_ps *boot_ps = rdev->pm.dpm
[all...]
H A Dsumo_dpm.c81 struct sumo_power_info *pi = rdev->pm.dpm.priv;
1172 rdev->pm.dpm.thermal.min_temp = low_temp;
1173 rdev->pm.dpm.thermal.max_temp = high_temp;
1230 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1275 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1281 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1420 rdev->pm.dpm.boot_ps = rps;
1424 rdev->pm.dpm.uvd_ps = rps;
1482 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
1485 if (!rdev->pm.dpm
[all...]
H A Dradeon_uvd.c866 radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd,
867 &rdev->pm.dpm.hd);
888 if ((rdev->pm.dpm.sd != sd) ||
889 (rdev->pm.dpm.hd != hd)) {
890 rdev->pm.dpm.sd = sd;
891 rdev->pm.dpm.hd = hd;
H A Dradeon.h1196 /* not used for dpm */
1643 /* dpm */
1646 struct radeon_dpm dpm; member in struct:radeon_pm
1984 } dpm; member in struct:radeon_asic
2760 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2761 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2762 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2763 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2764 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2765 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm
[all...]
H A Dradeon_drv.c203 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
204 module_param_named(dpm, radeon_dpm, int, 0444);
/linux-master/drivers/gpu/drm/amd/pm/
H A Damdgpu_dpm_internal.c36 adev->pm.dpm.new_active_crtcs = 0;
37 adev->pm.dpm.new_active_crtc_count = 0;
43 adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
44 adev->pm.dpm.new_active_crtc_count++;
H A DMakefile37 -I$(FULL_AMD_PATH)/pm/legacy-dpm
41 PM_LIBS = swsmu powerplay legacy-dpm
H A Damdgpu_dpm.c567 adev->pm.dpm.uvd_active = true;
568 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
570 adev->pm.dpm.uvd_active = false;
591 adev->pm.dpm.vce_active = true;
593 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
595 adev->pm.dpm.vce_active = false;
917 *state = adev->pm.dpm.user_state;
924 *state = adev->pm.dpm.user_state;
934 adev->pm.dpm.user_state = state;
958 level = adev->pm.dpm
[all...]
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhardwaremanager.c87 pr_info("dpm has been enabled\n");
107 pr_info("dpm has been disabled\n");
260 adev->pm.dpm.thermal.min_temp = range.min;
261 adev->pm.dpm.thermal.max_temp = range.max;
262 adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
263 adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
264 adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
265 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
266 adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
267 adev->pm.dpm
[all...]
/linux-master/drivers/net/can/
H A Djanz-ican3.c229 void __iomem *dpm; member in struct:ican3_dev
316 peer = ioread8(mod->dpm + MSYNC_PEER);
317 locl = ioread8(mod->dpm + MSYNC_LOCL);
334 memcpy_fromio(msg, mod->dpm, sizeof(*msg));
343 iowrite8(locl, mod->dpm + MSYNC_LOCL);
361 peer = ioread8(mod->dpm + MSYNC_PEER);
362 locl = ioread8(mod->dpm + MSYNC_LOCL);
376 memcpy_toio(mod->dpm, msg, sizeof(*msg));
383 iowrite8(locl, mod->dpm + MSYNC_LOCL);
406 dst = mod->dpm;
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