/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
H A D | display_rq_dlg_calc_32.c | 275 dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 276 dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8)); 345 ASSERT(dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); 441 dlg_regs->min_dst_y_next_start = min_dst_y_next_start * dml_pow(2, 2); 442 ASSERT(dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); 446 dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); 447 dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); 448 dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); 449 dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); 450 dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow( [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/ |
H A D | dml_display_rq_dlg_calc.c | 315 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (dml_uint_t)dml_pow(2, 13)); 317 disp_dlg_regs->ref_freq_to_pix_freq = (dml_uint_t)(ref_freq_to_pix_freq * dml_pow(2, 19)); 318 temp = dml_pow(2, 8); 411 disp_dlg_regs->min_dst_y_next_start = (dml_uint_t)((dml_float_t) min_dst_y_next_start * dml_pow(2, 2)); 412 ASSERT(disp_dlg_regs->min_dst_y_next_start < (dml_uint_t)dml_pow(2, 18)); 416 disp_dlg_regs->dst_y_prefetch = (dml_uint_t)(dst_y_prefetch * dml_pow(2, 2)); 417 disp_dlg_regs->dst_y_per_vm_vblank = (dml_uint_t)(dst_y_per_vm_vblank * dml_pow(2, 2)); 418 disp_dlg_regs->dst_y_per_row_vblank = (dml_uint_t)(dst_y_per_row_vblank * dml_pow(2, 2)); 419 disp_dlg_regs->dst_y_per_vm_flip = (dml_uint_t)(dst_y_per_vm_flip * dml_pow(2, 2)); 420 disp_dlg_regs->dst_y_per_row_flip = (dml_uint_t)(dst_y_per_row_flip * dml_pow( [all...] |
H A D | display_mode_util.h | 50 __DML_DLL_EXPORT__ dml_float_t dml_pow(dml_float_t base, int exp);
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H A D | display_mode_util.c | 196 dml_float_t dml_pow(dml_float_t base, int exp) function
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
H A D | display_rq_dlg_calc_21.c | 976 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 978 * dml_pow(2, 8)); 982 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); 991 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2)); 992 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); 1388 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); 1389 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 1424 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); 1425 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); 1469 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow( [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
H A D | display_rq_dlg_calc_20v2.c | 930 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 932 * dml_pow(2, 8)); 936 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); 946 + min_dst_y_ttu_vblank) * dml_pow(2, 2)); 947 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); 1325 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); 1326 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 1357 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); 1358 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); 1400 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow( [all...] |
H A D | display_rq_dlg_calc_20.c | 930 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 932 * dml_pow(2, 8)); 936 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); 945 disp_dlg_regs->min_dst_y_next_start = (unsigned int) ((double) dlg_vblank_start * dml_pow(2, 2)); 946 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); 1324 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); 1325 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 1356 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); 1357 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); 1399 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow( [all...] |
H A D | display_mode_vba_20v2.c | 313 / dml_pow( 3576 dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency 3599 dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency
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H A D | display_mode_vba_20.c | 289 / dml_pow( 3469 dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency 3492 dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
H A D | display_rq_dlg_calc_31.c | 831 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); 846 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); 981 disp_dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 982 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8)); 989 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2)); 991 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); 1096 } ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); 1335 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 1372 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow( [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
H A D | display_rq_dlg_calc_314.c | 917 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); 931 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); 1066 disp_dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 1067 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8)); 1076 disp_dlg_regs->min_dst_y_next_start = vba__min_dst_y_next_start * dml_pow(2, 2); 1078 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); 1184 } ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); 1423 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 1460 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow( [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
H A D | display_rq_dlg_calc_30.c | 854 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); 884 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); 1044 (unsigned int)(ref_freq_to_pix_freq * dml_pow(2, 19)); 1046 * dml_pow(2, 8)); 1057 ) * dml_pow(2, 2)); 1058 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18)); 1223 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13)); 1492 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); 1493 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 1524 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow( [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/ |
H A D | dml1_display_rq_dlg_calc.c | 1154 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 1156 * dml_pow(2, 8)); 1159 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); 1176 + min_dst_y_ttu_vblank) * dml_pow(2, 2)); 1177 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); 1441 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); 1451 disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); 1462 disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); 1466 disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); 1520 disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow( [all...] |
H A D | dml_inline_defs.h | 100 static inline double dml_pow(double a, int exp) function
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