Searched refs:dml_core_ctx (Results 1 - 6 of 6) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_wrapper.c73 if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&
74 dml2->v20.dml_core_ctx.project != dml_project_dcn351) {
99 s->mode_support_params.mode_lib = &dml2->v20.dml_core_ctx;
236 build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy);
261 for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) {
262 s->uclk_change_latencies[i] = dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us;
266 for (j = 0; j < dml2->v20.dml_core_ctx.states.num_states; j++) {
267 dml2->v20.dml_core_ctx.states.state_array[j].dram_clock_change_latency_us = s_global->dummy_pstate_table[i].dummy_pstate_latency_us;
274 dml_result = dml_mode_programming(&dml2->v20.dml_core_ctx, s_globa
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H A Ddml2_internal_types.h37 struct display_mode_lib_st *dml_core_ctx; member in struct:dml2_wrapper_optimize_configuration_params
118 struct display_mode_lib_st dml_core_ctx; member in struct:dml2_context::__anon124::__anon125
H A Ddml2_utils.c294 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (unsigned int)in_ctx->v20.dml_core_ctx.mp.DCFCLKDeepSleep * 1000;
297 if (in_ctx->v20.dml_core_ctx.ms.support.FCLKChangeSupport[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx] == dml_fclock_change_unsupported)
305 unbounded_req_enabled = in_ctx->v20.dml_core_ctx.ms.UnboundedRequestEnabledThisState;
313 context->bw_ctx.bw.dcn.compbuf_size_kb = in_ctx->v20.dml_core_ctx.ip.config_return_buffer_size_in_kbytes;
336 populate_pipe_ctx_dlg_params_from_dml(&context->res_ctx.pipe_ctx[dc_pipe_ctx_index], &context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);
344 context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb = dml_get_det_buffer_size_kbytes(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx);
349 context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000;
353 dml_rq_dlg_get_rq_reg(&s->rq_regs, &in_ctx->v20.dml_core_ctx, dml_pipe_idx);
354 dml_rq_dlg_get_dlg_reg(&s->disp_dlg_regs, &s->disp_ttu_regs, &in_ctx->v20.dml_core_ctx, dml_pipe_idx);
357 context->res_ctx.pipe_ctx[dc_pipe_ctx_index].surface_size_in_mall_bytes = dml_get_surface_size_for_mall(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_id
383 dml2_extract_watermark_set(struct dcn_watermarks *watermark, struct display_mode_lib_st *dml_core_ctx) argument
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H A Ddml2_utils.h42 void dml2_extract_watermark_set(struct dcn_watermarks *watermark, struct display_mode_lib_st *dml_core_ctx);
54 * result = dml_mode_programming(&in_ctx->dml_core_ctx, s->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true);
H A Ddml2_translation_helper.c35 switch (dml2->v20.dml_core_ctx.project) {
215 switch (dml2->v20.dml_core_ctx.project) {
264 switch (dml2->v20.dml_core_ctx.project) {
379 if ((dml2->v20.dml_core_ctx.project == dml_project_dcn32) ||
380 (dml2->v20.dml_core_ctx.project == dml_project_dcn321)) {
386 } else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&
387 dml2->v20.dml_core_ctx.project != dml_project_dcn351) {
435 if (dml2->v20.dml_core_ctx.project == dml_project_dcn35 ||
436 dml2->v20.dml_core_ctx.project == dml_project_dcn351) {
1071 dml_dispcfg->plane.GPUVMEnable = dml2->v20.dml_core_ctx
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H A Ddml2_mall_phantom.c902 vstartup = dml_get_vstartup_calculated(&ctx->v20.dml_core_ctx, dml_pipe_idx);

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