Searched refs:dml_ceil (Results 1 - 24 of 24) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_mode_vba_21.c755 *VUpdateOffsetPix = dml_ceil(myPipe->HTotal / 4.0, 1);
808 *swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockWidth256BytesY) + myPipe->BlockWidth256BytesY;
810 *swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockWidth256BytesC) + myPipe->BlockWidth256BytesC;
812 *swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockHeight256BytesY) + myPipe->BlockHeight256BytesY;
814 *swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockHeight256BytesC) + myPipe->BlockHeight256BytesC;
817 prefetch_bw_oto = (PrefetchSourceLinesY * *swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) + PrefetchSourceLinesC * *swath_width_chroma_ub * dml_ceil(BytePerPixelDETC, 2)) / Tsw_oto;
834 Tvm_oto_lines = dml_ceil(4 * Tvm_oto / LineTime, 1) / 4.0;
835 Tr0_oto_lines = dml_ceil(4 * Tr0_oto / LineTime, 1) / 4.0;
836 Tsw_oto_lines = dml_ceil(
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H A Ddisplay_rq_dlg_calc_21.c451 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
687 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil(
1753 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_util_32.c222 dml_ceil((double) HTaps / 6.0, 1.0));
240 HRatioChroma / dml_ceil((double) HTapsChroma / 6.0, 1.0));
533 RoundedUpMaxSwathSizeBytesY[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesY[k], 256);
534 RoundedUpMaxSwathSizeBytesC[k] = dml_ceil((unsigned int) RoundedUpMaxSwathSizeBytesC[k], 256);
787 surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);
788 surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);
803 dml_ceil(SwathWidthY[k] - 1,
808 surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);
818 dml_ceil(SwathWidthC[k] - 1,
835 swath_width_luma_ub[k] = dml_min(surface_height_ub_l, dml_ceil(SwathWidth
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H A Ddisplay_rq_dlg_calc_32.c294 dst_x_after_scaler = dml_ceil(get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx), 1);
295 dst_y_after_scaler = dml_ceil(get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx), 1);
H A Ddisplay_mode_vba_32.c700 dml_ceil((double) v->WritebackDelay[mode_lib->vba.VoltageLevel][k]
1446 dml_ceil(v->WritebackDelay[mode_lib->vba.VoltageLevel][k]
1833 v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0)
1835 v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0)
1940 / (mode_lib->vba.vtaps[k] + dml_max(dml_ceil(mode_lib->vba.VRatio[k], 1.0) - 2, 0.0));
1947 + dml_max(dml_ceil(mode_lib->vba.VRatioChroma[k], 1.0) - 2,
2967 - dml_max(1.0, dml_ceil(1.0 *
3628 mode_lib->vba.AlignedYPitch[k] = dml_ceil(
3632 mode_lib->vba.AlignedDCCMetaPitchY[k] = dml_ceil(
3643 mode_lib->vba.AlignedCPitch[k] = dml_ceil(
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_mode_vba_20v2.c503 DataFabricLineDeliveryTimeLuma = SwathWidthSingleDPPY * SwathHeightY * dml_ceil(BytePerPixelDETY, 1) / (mode_lib->vba.ReturnBW * ReadBandwidthPlaneLuma / TotalDataReadBandwidth);
507 DataFabricLineDeliveryTimeChroma = SwathWidthSingleDPPY / 2 * SwathHeightC * dml_ceil(BytePerPixelDETC, 2) / (mode_lib->vba.ReturnBW * ReadBandwidthPlaneChroma / TotalDataReadBandwidth);
609 *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1);
661 + PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1)
662 + PrefetchSourceLinesC * SwathWidthY / 2 * dml_ceil(BytePerPixelDETC, 2))
717 + PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1)
719 * dml_ceil(BytePerPixelDETC, 2))
825 * dml_ceil(
830 * dml_ceil(
869 return VCOSpeed * 4 / dml_ceil(VCOSpee
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H A Ddisplay_mode_vba_20.c546 *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1);
601 + PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1)
602 + PrefetchSourceLinesC * SwathWidthY / 2 * dml_ceil(BytePerPixelDETC, 2))
657 + PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1)
659 * dml_ceil(BytePerPixelDETC, 2))
765 * dml_ceil(
770 * dml_ceil(
809 return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4 / Clock, 1);
832 *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0;
847 *MaxNumSwath = dml_ceil(*VInitPreFil
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H A Ddisplay_rq_dlg_calc_20v2.c459 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
680 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
1640 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
H A Ddisplay_rq_dlg_calc_20.c459 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
680 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
1639 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
/linux-master/drivers/gpu/drm/amd/display/dc/dml/
H A Ddml_inline_defs.h67 static inline double dml_ceil(double a, double granularity) function
H A Ddisplay_mode_vba.c1126 dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio,
1127 dml_max((WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1) * dml_ceil(WritebackDestinationWidth / 4.0, 1)
1128 + dml_ceil(WritebackDestinationWidth / 4.0, 1)) / (double) HTotal + dml_ceil(1.0 / WritebackVRatio, 1)
1129 * (dml_ceil(WritebackLumaVTaps / 4.0, 1) + 4.0) / (double) HTotal,
1130 dml_ceil(1.0 / WritebackVRatio, 1) * WritebackDestinationWidth / (double) HTotal));
1133 dml_ceil(WritebackChromaHTaps / 2.0, 1) / (2 * WritebackHRatio),
1134 dml_max((WritebackChromaVTaps * dml_ceil(1 / (2 * WritebackVRatio), 1) * dml_ceil(WritebackDestinationWidt
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H A Ddml1_display_rq_dlg_calc.c185 *max_num_sw = (unsigned int) (dml_ceil((prefill - 1.0) / (double) swath_height, 1) + 1.0); /* prefill has to be >= 1 */
447 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
687 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
923 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil(
1851 cur0_width_ub = dml_ceil((double) cur0_src_width / (double) cur0_req_width, 1)
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_mode_vba_31.c1025 Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1) / 4 * LineTime;
1026 Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1) / 4 * LineTime;
1064 Lsw_oto = dml_ceil(4 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1) / 4;
1104 Tvm_oto_lines = dml_ceil(4.0 * Tvm_oto / LineTime, 1) / 4.0;
1105 Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0;
1280 *DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0;
1282 *DestinationLinesToRequestRowInVBlank = dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0;
1469 return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4.0 / Clock, 1);
1590 full_swath_bytes_horz_wc_l = dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256);
1591 full_swath_bytes_horz_wc_c = dml_ceil(full_swath_bytes_horz_wc_
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H A Ddisplay_rq_dlg_calc_31.c425 log2_blk_height = log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
646 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1);
821 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_mode_vba_314.c1046 Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1) / 4 * LineTime;
1047 Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1) / 4 * LineTime;
1085 Lsw_oto = dml_ceil(4 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1) / 4;
1125 Tvm_oto_lines = dml_ceil(4.0 * Tvm_oto / LineTime, 1) / 4.0;
1126 Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0;
1301 *DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0;
1303 *DestinationLinesToRequestRowInVBlank = dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0;
1489 return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4.0 / Clock, 1);
1610 full_swath_bytes_horz_wc_l = dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256);
1611 full_swath_bytes_horz_wc_c = dml_ceil(full_swath_bytes_horz_wc_
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H A Ddcn314_fpu.c291 num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0);
H A Ddisplay_rq_dlg_calc_314.c513 log2_blk_height = log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
734 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1);
908 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c990 Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1) / 4 * LineTime;
991 Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1) / 4 * LineTime;
1025 Tvm_oto_lines = dml_ceil(4.0 * Tvm_oto / LineTime, 1) / 4.0;
1026 Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0;
1188 *DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0;
1190 *DestinationLinesToRequestRowInVBlank = dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0;
1305 return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4.0 / Clock, 1);
1447 full_swath_bytes_horz_wc_l = dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256);
1448 full_swath_bytes_horz_wc_c = dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256);
1449 full_swath_bytes_vert_wc_l = dml_ceil(full_swath_bytes_vert_wc_
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H A Ddisplay_rq_dlg_calc_30.c405 + dml_ceil((double)(log2_blk_bytes - 8) / 2.0, 1);
651 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double)dpte_row_width_ub / dpte_group_width,
840 cur_width_ub = dml_ceil((double)cur_src_width / (double)cur_req_width, 1)
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddisplay_mode_util.h38 __DML_DLL_EXPORT__ dml_float_t dml_ceil(dml_float_t x, dml_float_t granularity);
H A Ddisplay_mode_core.c1153 s->Tvm_trips_rounded = dml_ceil(4.0 * s->Tvm_trips / s->LineTime, 1.0) / 4.0 * s->LineTime;
1154 s->Tr0_trips_rounded = dml_ceil(4.0 * s->Tr0_trips / s->LineTime, 1.0) / 4.0 * s->LineTime;
1158 s->Tr0_trips_rounded = dml_ceil(4.0 * p->UrgentExtraLatency / s->LineTime, 1.0) / 4.0 * s->LineTime;
1165 s->Tr0_trips_rounded = dml_ceil(4.0 * s->Tr0_trips / s->LineTime, 1.0) / 4.0 * s->LineTime;
1192 s->Lsw_oto = dml_ceil(4.0 * dml_max(s->prefetch_sw_bytes / s->prefetch_bw_oto / s->LineTime, s->min_Lsw_oto), 1.0) / 4.0;
1217 s->Tvm_oto_lines = dml_ceil(4.0 * s->Tvm_oto / s->LineTime, 1) / 4.0;
1218 s->Tr0_oto_lines = dml_ceil(4.0 * s->Tr0_oto / s->LineTime, 1) / 4.0;
1411 *p->DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * s->TimeForFetchingMetaPTE / s->LineTime, 1.0) / 4.0;
1412 *p->DestinationLinesToRequestRowInVBlank = dml_ceil(4.0 * s->TimeForFetchingRowInVBlank / s->LineTime, 1.0) / 4.0;
1422 *p->DestinationLinesToRequestVMInVBlank = dml_ceil(4.
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H A Ddisplay_mode_util.c108 dml_float_t dml_ceil(dml_float_t x, dml_float_t granularity) function
186 double ceil = dml_ceil(val, 1);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c419 num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c454 num_lines = dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0);

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