Searched refs:div_l (Results 1 - 5 of 5) sorted by relevance

/linux-master/drivers/clk/bcm/
H A Dclk-iproc-asiu.c74 unsigned int div_h, div_l; local
91 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width);
92 div_l++;
94 clk->rate = parent_rate / (div_h + div_l);
95 pr_debug("%s: rate: %lu. parent rate: %lu div_h: %u div_l: %u\n",
96 __func__, clk->rate, parent_rate, div_h, div_l);
124 unsigned int div, div_h, div_l; local
142 div_h = div_l = div >> 1;
144 div_l--;
156 if (div_l) {
[all...]
/linux-master/drivers/hwmon/
H A Daspeed-g6-pwm-tach.c157 u64 div_h, div_l, duty_cycle_period, dividend; local
164 div_l = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_L, val);
172 dividend = (u64)NSEC_PER_SEC * (div_l + 1) * (duty_cycle_period + 1)
177 dividend = (u64)NSEC_PER_SEC * (div_l + 1) * duty_pt
193 u64 div_h, div_l, divisor, expect_period; local
201 * Pick the smallest value for div_h so that div_l can be the biggest
211 div_l = div64_u64(priv->clk_rate * expect_period, divisor);
213 if (div_l == 0)
216 div_l -= 1;
218 if (div_l > 25
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H A Daspeed-pwm-tacho.c508 u8 clk_unit, div_h, div_l, tacho_div; local
514 div_l = priv->type_pwm_clock_division_l[type];
515 if (div_l == 0)
516 div_l = 1;
518 div_l = div_l * 2;
524 return clk / (clk_unit * div_h * div_l * tacho_div * tacho_unit);
/linux-master/drivers/i2c/busses/
H A Di2c-meson.c142 unsigned int div_h, div_l; local
153 div_l = DIV_ROUND_UP(div_h, 4);
157 div_l = DIV_ROUND_UP(clk_rate * 3, freq * 5 * 2);
165 if (div_l > GENMASK(11, 0)) {
167 div_l = GENMASK(11, 0);
178 FIELD_PREP(REG_SLV_SCL_LOW_MASK, div_l));
184 clk_rate, freq, div_h, div_l);
/linux-master/drivers/tty/serial/
H A Dsunplus-uart.c336 u32 ext, div, div_l, div_h, baud, lcr; local
347 div_l = (div & 0xFF) | (ext << 12);
407 writel(div_l, port->membase + SUP_UART_DIV_L);

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