Lines Matching refs:div_l
156 u64 div_h, div_l, duty_cycle_period, dividend;
163 div_l = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_L, val);
171 dividend = (u64)NSEC_PER_SEC * (div_l + 1) * (duty_cycle_period + 1)
176 dividend = (u64)NSEC_PER_SEC * (div_l + 1) * duty_pt
192 u64 div_h, div_l, divisor, expect_period;
200 * Pick the smallest value for div_h so that div_l can be the biggest
210 div_l = div64_u64(priv->clk_rate * expect_period, divisor);
212 if (div_l == 0)
215 div_l -= 1;
217 if (div_l > 255)
218 div_l = 255;
220 dev_dbg(pwmchip_parent(chip), "clk source: %ld div_h %lld, div_l : %lld\n",
221 priv->clk_rate, div_h, div_l);
224 (u64)NSEC_PER_SEC * (div_l + 1) << div_h);
258 FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) |