Searched refs:div1 (Results 1 - 25 of 27) sorted by relevance

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/linux-master/arch/sh/lib/
H A Dudivsi3.S16 div1 r5,r4
18 div1 r5,r4; div1 r5,r4; div1 r5,r4
19 div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
22 div1 r5,r4; rotcl r0
23 div1 r
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H A Dudivsi3_i4i-Os.S38 div1 r5,r4
40 div1 r5,r4
41 div1 r5,r4
43 div1 r5,r4
48 div1 r5,r4
50 div1 r5,r4
58 div1 r5,r4
60 div1 r5,r4; div1 r5,r4; div1 r
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H A Ddiv64.S26 div1 r6, r3
36 div1 r6, r1
H A Dudivsi3_i4i.S24 div1 with case distinction for larger divisors in three more ranges.
55 div1 r5,r0
57 div1 r5,r0
58 div1 r5,r0
60 div1 r5,r0
102 div1 r5,r0
109 div1 r5,r0
112 div1 r5,r0
115 div1 r5,r0
118 div1 r
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H A Dudiv_qrnnd.S29 div1 r6,r0
/linux-master/drivers/clk/samsung/
H A Dclk-cpu.h34 * @div1: value to be programmed in the div_cpu1 register
39 * For CPU clock domains that do not have a DIV1 register, the @div1 member
45 unsigned long div1; member in struct:exynos_cpuclk_cfg_data
H A Dclk-cpu.c203 unsigned long div0, div1 = 0, mux_reg; local
222 div1 = cfg_data->div1;
224 div1 = readl(base + regs->div_cpu1) &
265 writel(div1, base + regs->div_cpu1);
330 unsigned long div0, div1 = 0, mux_reg; local
347 div1 = cfg_data->div1;
377 writel(div1, base + regs->div_cpu1);
/linux-master/drivers/clk/
H A Dclk-vt8500.c456 int div1, div2; local
462 for (div1 = 1; div1 >= 0; div1--)
465 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2));
471 *filter = wm8750_get_filter(parent_rate, div1);
473 *divisor1 = div1;
481 *divisor1 = div1;
504 int div1, div2; local
510 for (div1
550 u32 filter, mul, div1, div2; local
601 u32 filter, mul, div1, div2; local
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/linux-master/drivers/clk/uniphier/
H A Dclk-uniphier.h110 #define UNIPHIER_CLK_DIV2(parent, div0, div1) \
112 UNIPHIER_CLK_DIV(parent, div1)
114 #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \
115 UNIPHIER_CLK_DIV2(parent, div0, div1), \
118 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \
119 UNIPHIER_CLK_DIV2(parent, div0, div1), \
122 #define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \
123 UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3), \
/linux-master/arch/microblaze/lib/
H A Ddivsi3.S39 div1: label
41 bgtid r5, div1
H A Dmodsi3.S39 div1: label
41 bgeid r5, div1
H A Dudivsi3.S53 div1: label
55 bgtid r5, div1
H A Dumodsi3.S55 div1: label
57 bgeid r5, div1
/linux-master/drivers/clk/imx/
H A Dclk-composite-8m.c54 int div1, div2; local
61 for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
63 int new_error = ((parent_rate / div1) / div2) - rate;
66 *prediv = div1;
/linux-master/drivers/spi/
H A Dspi-omap-uwire.c314 int div1; local
359 div1 = 2;
362 div1 = 4;
365 div1 = 7;
369 div1 = 10;
372 div2 = (rate / div1 + hz - 1) / hz;
389 rate /= div1;
/linux-master/drivers/media/tuners/
H A Dmt2131.c89 u32 div1, num1, div2, num2; local
106 div1 = num1 / 8192;
137 b[3] = div1;
145 dprintk(1, "PLL div1=%d num1=%d div2=%d num2=%d\n",
146 (int)div1, (int)num1, (int)div2, (int)num2);
H A Dmt2060.c196 u32 div1,num1,div2,num2; local
228 div1 = num1 / 64;
249 b[2] = div1;
256 dprintk("PLL div1=%d num1=%d div2=%d num2=%d",(int)div1,(int)num1,(int)div2,(int)num2);
/linux-master/arch/mips/alchemy/common/
H A Dclock.c379 long div1, div2; local
381 div1 = prate / rate;
382 if ((prate / div1) > rate)
383 div1++;
386 if (div1 & 1)
387 div1++; /* stay <=prate */
390 div2 = (div1 / scale) - 1; /* value to write to register */
397 div1 = ((div2 + 1) * scale);
398 return div1;
/linux-master/drivers/i2c/busses/
H A Di2c-s3c2410.c812 unsigned int *div1, unsigned int *divs)
831 *div1 = calc_div1;
845 unsigned int divs, div1; local
859 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
874 if (div1 == 512)
811 s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, unsigned int *div1, unsigned int *divs) argument
H A Di2c-sprd.c339 u32 div1 = I2C_ADDR_DVD1_CALC(high, low); local
342 writel(div1, i2c_dev->base + ADDR_DVD1);
/linux-master/drivers/clk/x86/
H A Dclk-cgu.c395 unsigned int div0, div1, exdiv; local
400 div1 = lgm_get_clk_val(ddiv->membase, ddiv->reg,
406 do_div(prate, div1);
/linux-master/drivers/media/dvb-frontends/
H A Dstb0899_algo.c1274 int div1, div2, rem1, rem2; local
1276 div1 = config->btr_nco_bits / 2;
1277 div2 = config->btr_nco_bits - div1 - 1;
1285 intval1 = internal->master_clk / (1 << div1);
1288 rem1 = internal->master_clk % (1 << div1);
1291 srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
/linux-master/drivers/comedi/drivers/
H A Dadl_pci9118.c532 unsigned int *div1, unsigned int *div2,
538 *div1 = *tim2 / pacer->osc_base; /* convert timer (burst) */
540 *div2 = *div2 / *div1; /* major timer is c1*c2 */
544 *tim2 = *div1 * pacer->osc_base; /* real convert timer */
552 *tim1 = *div1 * *div2 * pacer->osc_base;
528 pci9118_calc_divisors(struct comedi_device *dev, struct comedi_subdevice *s, unsigned int *tim1, unsigned int *tim2, unsigned int flags, int chans, unsigned int *div1, unsigned int *div2, unsigned int chnsshfront) argument
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.c2879 int div1 = div1_vals[i]; local
2882 int dco = div1 * div2 * clock_khz * 5;
2903 switch (div1) {
2905 MISSING_CASE(div1);
3152 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; local
3185 div1 = 2;
3188 div1 = 3;
3191 div1 = 5;
3194 div1 = 7;
3215 tmp = div_u64(tmp, 5 * div1 * div
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/linux-master/sound/soc/codecs/
H A Dda7210.c214 u8 div1; member in struct:pll_div
1004 pll_div1 = da7210_pll_div[cnt].div1;

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