Searched refs:dct (Results 1 - 13 of 13) sorted by relevance

/linux-master/drivers/infiniband/hw/mlx5/
H A Dqpc.c13 struct mlx5_core_dct *dct);
93 struct mlx5_core_dct *dct; local
97 qpn = be32_to_cpu(eqe->data.dct.dctn) & 0xFFFFFF;
99 dct = xa_load(&dev->qp_table.dct_xa, qpn);
100 if (dct)
101 complete(&dct->drained);
196 struct mlx5_core_dct *dct)
199 struct mlx5_core_qp *qp = &dct->mqp;
207 int mlx5_core_create_dct(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct, argument
210 struct mlx5_core_qp *qp = &dct
195 _mlx5_core_destroy_dct(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct) argument
264 mlx5_core_drain_dct(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct) argument
276 mlx5_core_destroy_dct(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct) argument
535 mlx5_core_dct_query(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct, u32 *out, int outlen) argument
[all...]
H A Dqp.h31 int mlx5_core_destroy_dct(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct);
34 int mlx5_core_dct_query(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct,
H A Dqp.c2741 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2742 if (!qp->dct.in)
2745 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2746 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2769 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct))
3195 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct);
3202 kfree(mqp->dct.in);
4508 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
4581 err = mlx5_core_create_dct(dev, &qp->dct.mdct, qp->dct
5001 struct mlx5_core_dct *dct = &mqp->dct.mdct; local
[all...]
H A Ddevx.c653 qp->dct.mdct.mqp.qpn) == obj_id;
2435 obj_id = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff;
H A Dmlx5_ib.h500 struct mlx5_ib_dct dct; member in union:mlx5_ib_qp::__anon58
/linux-master/drivers/edac/
H A Damd64_edac.c103 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) argument
109 reg |= dct;
127 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, argument
132 if (dct || offset >= 0x100)
137 if (dct) {
155 dct = (dct && pvt->model == 0x30) ? 3 : dct;
156 f15h_select_dct(pvt, dct);
160 if (dct)
373 get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, u64 *base, u64 *mask) argument
1845 k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, unsigned cs_mode, int cs_mask_nr) argument
1949 f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, unsigned cs_mode, int cs_mask_nr) argument
1965 f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, unsigned cs_mode, int cs_mask_nr) argument
1974 f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, unsigned cs_mode, int cs_mask_nr) argument
2007 f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, unsigned cs_mode, int cs_mask_nr) argument
2179 f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) argument
2204 f1x_lookup_addr_in_dct(u64 in_addr, u8 nid, u8 dct) argument
3029 dct_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) argument
3047 umc_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig) argument
3562 gpu_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) argument
3986 int cs = 0, dct = 0; local
[all...]
H A Damd64_edac.h166 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
167 #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
468 int (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct,
/linux-master/drivers/soc/fsl/dpio/
H A Dqbman-portal.h215 enum qbman_pull_type_e dct);
217 enum qbman_pull_type_e dct);
H A Dqbman-portal.c1065 * @dct: the dequeue command type
1068 enum qbman_pull_type_e dct)
1070 d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
1080 * @dct: the dequeue command type
1083 enum qbman_pull_type_e dct)
1085 d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
1067 qbman_pull_desc_set_wq(struct qbman_pull_desc *d, u32 wqid, enum qbman_pull_type_e dct) argument
1082 qbman_pull_desc_set_channel(struct qbman_pull_desc *d, u32 chid, enum qbman_pull_type_e dct) argument
/linux-master/drivers/net/ethernet/mellanox/mlx5/core/
H A Dmain.c614 if (MLX5_CAP_GEN_MAX(dev, dct))
615 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
H A Deq.c571 if (MLX5_CAP_GEN_MAX(dev, dct))
/linux-master/include/linux/mlx5/
H A Ddevice.h752 struct mlx5_eqe_dct dct; member in union:ev_data
H A Dmlx5_ifc.h1661 u8 dct[0x1]; member in struct:mlx5_ifc_cmd_hca_cap_bits

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