Searched refs:dcf_deep_sleep_divider (Results 1 - 3 of 3) sorted by last modified time

/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c316 regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
343 regs_and_bypass->dcf_deep_sleep_divider,
382 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c248 regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
275 regs_and_bypass->dcf_deep_sleep_divider,
314 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h54 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
74 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
90 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
175 uint32_t dcf_deep_sleep_divider; member in struct:clk_state_registers_and_bypass
190 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider
205 uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider
218 uint32_t CLK0_CLK8_DS_CNTL; //dcf_deep_sleep_divider

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