| /freebsd-11-stable/secure/lib/libcrypto/arm/ |
| H A D | sha512-armv4.S | 455 vldmia r0,{d16-d23} @ load context
463 vadd.i64 d16,d30 @ h+=Maj from the past
476 vshr.u64 d24,d16,#28
479 vshr.u64 d25,d16,#34
480 vsli.64 d24,d16,#36
482 vshr.u64 d26,d16,#39
484 vsli.64 d25,d16,#30
485 veor d30,d16,d17
486 vsli.64 d26,d16,#25
522 veor d30,d23,d16
[all...] |
| H A D | ghash-armv4.S | 328 vshr.u64 d16,#63 @ t0=0xc2....01
382 vext.8 d16, d26, d26, #1 @ A1
383 vmull.p8 q8, d16, d6 @ F = A1*B
396 veor d16, d16, d17 @ t0 = (L) (P0 + P1) << 8
403 veor d16, d16, d17
420 vext.8 d16, d28, d28, #1 @ A1
421 vmull.p8 q8, d16, d6 @ F = A1*B
434 veor d16, d1
[all...] |
| H A D | armv4-gf2m.S | 159 vext.8 d16, d27, d27, #2 @ B2
160 vmull.p8 q8, d26, d16 @ G = A*B2
169 vext.8 d16, d27, d27, #4 @ B4
172 vmull.p8 q8, d26, d16 @ K = A*B4
179 veor d16, d16, d17 @ t3 = (K) (P6 + P7) << 32
|
| H A D | aesv8-armx.S | 103 vld1.8 {d16},[r0]!
112 vst1.32 {d16},[r2]!
|
| H A D | sha1-armv4-large.S | 1333 vld1.32 {d16[],d17[]},[r3,:32]!
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIAddIMGInit.cpp | 81 MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16);
|
| H A D | SILoadStoreOptimizer.cpp | 284 // FIXME: Handle d16 correctly
673 AMDGPU::OpName::d16, AMDGPU::OpName::unorm,
1420 // FIXME: Handle d16 correctly
|
| H A D | SIInstrInfo.cpp | 3410 const MachineOperand *D16 = getNamedOperand(MI, AMDGPU::OpName::d16);
|
| H A D | SIISelLowering.cpp | 10131 int D16Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::d16) - 1;
|
| /freebsd-11-stable/contrib/llvm-project/libunwind/src/ |
| H A D | UnwindRegistersRestore.S | 596 ldp d16,d17, [x0, #0x190]
667 .fpu vfpv3-d16
688 .fpu vfpv3-d16
705 vldmia r0, {d16-d31}
|
| H A D | UnwindRegistersSave.S | 738 stp d16,d17, [x0, #0x190]
811 .fpu vfpv3-d16
825 .fpu vfpv3-d16
849 vstmia r0, {d16-d31}
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86Disassembler.cpp | 571 int16_t d16; local
585 if (consume(insn, d16))
587 insn->displacement = d16;
|
| /freebsd-11-stable/sys/dev/bwn/ |
| H A D | if_bwnvar.h | 833 uint16_t d16; member in union:bwn_fwinitvals::__anon25
|
| H A D | if_bwn.c | 4320 if (array_size < sizeof(iv->data.d16))
4322 array_size -= sizeof(iv->data.d16);
4323 BWN_WRITE_2(mac, offset, be16toh(iv->data.d16));
|
| /freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
| H A D | RegisterInfos_arm64.h | 695 DEFINE_FPU_PSEUDO(d16, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v16),
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 478 AMDGPU::OpName::d16);
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2966 int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16);
3096 int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16);
3478 // For MUBUF/MTBUF d16 is a part of opcode, so there is nothing to validate.
3481 "d16 modifier is not supported on this GPU");
6092 {"d16", AMDGPUOperand::ImmTyD16, true, nullptr},
6101 {"d16", AMDGPUOperand::ImmTyD16, true, nullptr},
|