1/*- 2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/11/sys/dev/bwn/if_bwn.c 345636 2019-03-28 09:50:25Z avos $"); 32 33/* 34 * The Broadcom Wireless LAN controller driver. 35 */ 36 37#include "opt_bwn.h" 38#include "opt_wlan.h" 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> 43#include <sys/malloc.h> 44#include <sys/module.h> 45#include <sys/endian.h> 46#include <sys/errno.h> 47#include <sys/firmware.h> 48#include <sys/lock.h> 49#include <sys/mutex.h> 50#include <machine/bus.h> 51#include <machine/resource.h> 52#include <sys/bus.h> 53#include <sys/rman.h> 54#include <sys/socket.h> 55#include <sys/sockio.h> 56 57#include <net/ethernet.h> 58#include <net/if.h> 59#include <net/if_var.h> 60#include <net/if_arp.h> 61#include <net/if_dl.h> 62#include <net/if_llc.h> 63#include <net/if_media.h> 64#include <net/if_types.h> 65 66#include <dev/pci/pcivar.h> 67#include <dev/pci/pcireg.h> 68#include <dev/siba/siba_ids.h> 69#include <dev/siba/sibareg.h> 70#include <dev/siba/sibavar.h> 71 72#include <net80211/ieee80211_var.h> 73#include <net80211/ieee80211_radiotap.h> 74#include <net80211/ieee80211_regdomain.h> 75#include <net80211/ieee80211_phy.h> 76#include <net80211/ieee80211_ratectl.h> 77 78#include <dev/bwn/if_bwnreg.h> 79#include <dev/bwn/if_bwnvar.h> 80 81#include <dev/bwn/if_bwn_debug.h> 82#include <dev/bwn/if_bwn_misc.h> 83#include <dev/bwn/if_bwn_util.h> 84#include <dev/bwn/if_bwn_phy_common.h> 85#include <dev/bwn/if_bwn_phy_g.h> 86#include <dev/bwn/if_bwn_phy_lp.h> 87#include <dev/bwn/if_bwn_phy_n.h> 88 89static SYSCTL_NODE(_hw, OID_AUTO, bwn, CTLFLAG_RD, 0, 90 "Broadcom driver parameters"); 91 92/* 93 * Tunable & sysctl variables. 94 */ 95 96#ifdef BWN_DEBUG 97static int bwn_debug = 0; 98SYSCTL_INT(_hw_bwn, OID_AUTO, debug, CTLFLAG_RWTUN, &bwn_debug, 0, 99 "Broadcom debugging printfs"); 100#endif 101 102static int bwn_bfp = 0; /* use "Bad Frames Preemption" */ 103SYSCTL_INT(_hw_bwn, OID_AUTO, bfp, CTLFLAG_RW, &bwn_bfp, 0, 104 "uses Bad Frames Preemption"); 105static int bwn_bluetooth = 1; 106SYSCTL_INT(_hw_bwn, OID_AUTO, bluetooth, CTLFLAG_RW, &bwn_bluetooth, 0, 107 "turns on Bluetooth Coexistence"); 108static int bwn_hwpctl = 0; 109SYSCTL_INT(_hw_bwn, OID_AUTO, hwpctl, CTLFLAG_RW, &bwn_hwpctl, 0, 110 "uses H/W power control"); 111static int bwn_msi_disable = 0; /* MSI disabled */ 112TUNABLE_INT("hw.bwn.msi_disable", &bwn_msi_disable); 113static int bwn_usedma = 1; 114SYSCTL_INT(_hw_bwn, OID_AUTO, usedma, CTLFLAG_RD, &bwn_usedma, 0, 115 "uses DMA"); 116TUNABLE_INT("hw.bwn.usedma", &bwn_usedma); 117static int bwn_wme = 1; 118SYSCTL_INT(_hw_bwn, OID_AUTO, wme, CTLFLAG_RW, &bwn_wme, 0, 119 "uses WME support"); 120 121static void bwn_attach_pre(struct bwn_softc *); 122static int bwn_attach_post(struct bwn_softc *); 123static void bwn_sprom_bugfixes(device_t); 124static int bwn_init(struct bwn_softc *); 125static void bwn_parent(struct ieee80211com *); 126static void bwn_start(struct bwn_softc *); 127static int bwn_transmit(struct ieee80211com *, struct mbuf *); 128static int bwn_attach_core(struct bwn_mac *); 129static int bwn_phy_getinfo(struct bwn_mac *, int); 130static int bwn_chiptest(struct bwn_mac *); 131static int bwn_setup_channels(struct bwn_mac *, int, int); 132static void bwn_shm_ctlword(struct bwn_mac *, uint16_t, 133 uint16_t); 134static void bwn_addchannels(struct ieee80211_channel [], int, int *, 135 const struct bwn_channelinfo *, const uint8_t []); 136static int bwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 137 const struct ieee80211_bpf_params *); 138static void bwn_updateslot(struct ieee80211com *); 139static void bwn_update_promisc(struct ieee80211com *); 140static void bwn_wme_init(struct bwn_mac *); 141static int bwn_wme_update(struct ieee80211com *); 142static void bwn_wme_clear(struct bwn_softc *); 143static void bwn_wme_load(struct bwn_mac *); 144static void bwn_wme_loadparams(struct bwn_mac *, 145 const struct wmeParams *, uint16_t); 146static void bwn_scan_start(struct ieee80211com *); 147static void bwn_scan_end(struct ieee80211com *); 148static void bwn_set_channel(struct ieee80211com *); 149static struct ieee80211vap *bwn_vap_create(struct ieee80211com *, 150 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 151 const uint8_t [IEEE80211_ADDR_LEN], 152 const uint8_t [IEEE80211_ADDR_LEN]); 153static void bwn_vap_delete(struct ieee80211vap *); 154static void bwn_stop(struct bwn_softc *); 155static int bwn_core_init(struct bwn_mac *); 156static void bwn_core_start(struct bwn_mac *); 157static void bwn_core_exit(struct bwn_mac *); 158static void bwn_bt_disable(struct bwn_mac *); 159static int bwn_chip_init(struct bwn_mac *); 160static void bwn_set_txretry(struct bwn_mac *, int, int); 161static void bwn_rate_init(struct bwn_mac *); 162static void bwn_set_phytxctl(struct bwn_mac *); 163static void bwn_spu_setdelay(struct bwn_mac *, int); 164static void bwn_bt_enable(struct bwn_mac *); 165static void bwn_set_macaddr(struct bwn_mac *); 166static void bwn_crypt_init(struct bwn_mac *); 167static void bwn_chip_exit(struct bwn_mac *); 168static int bwn_fw_fillinfo(struct bwn_mac *); 169static int bwn_fw_loaducode(struct bwn_mac *); 170static int bwn_gpio_init(struct bwn_mac *); 171static int bwn_fw_loadinitvals(struct bwn_mac *); 172static int bwn_phy_init(struct bwn_mac *); 173static void bwn_set_txantenna(struct bwn_mac *, int); 174static void bwn_set_opmode(struct bwn_mac *); 175static void bwn_rate_write(struct bwn_mac *, uint16_t, int); 176static uint8_t bwn_plcp_getcck(const uint8_t); 177static uint8_t bwn_plcp_getofdm(const uint8_t); 178static void bwn_pio_init(struct bwn_mac *); 179static uint16_t bwn_pio_idx2base(struct bwn_mac *, int); 180static void bwn_pio_set_txqueue(struct bwn_mac *, struct bwn_pio_txqueue *, 181 int); 182static void bwn_pio_setupqueue_rx(struct bwn_mac *, 183 struct bwn_pio_rxqueue *, int); 184static void bwn_destroy_queue_tx(struct bwn_pio_txqueue *); 185static uint16_t bwn_pio_read_2(struct bwn_mac *, struct bwn_pio_txqueue *, 186 uint16_t); 187static void bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *); 188static int bwn_pio_rx(struct bwn_pio_rxqueue *); 189static uint8_t bwn_pio_rxeof(struct bwn_pio_rxqueue *); 190static void bwn_pio_handle_txeof(struct bwn_mac *, 191 const struct bwn_txstatus *); 192static uint16_t bwn_pio_rx_read_2(struct bwn_pio_rxqueue *, uint16_t); 193static uint32_t bwn_pio_rx_read_4(struct bwn_pio_rxqueue *, uint16_t); 194static void bwn_pio_rx_write_2(struct bwn_pio_rxqueue *, uint16_t, 195 uint16_t); 196static void bwn_pio_rx_write_4(struct bwn_pio_rxqueue *, uint16_t, 197 uint32_t); 198static int bwn_pio_tx_start(struct bwn_mac *, struct ieee80211_node *, 199 struct mbuf **); 200static struct bwn_pio_txqueue *bwn_pio_select(struct bwn_mac *, uint8_t); 201static uint32_t bwn_pio_write_multi_4(struct bwn_mac *, 202 struct bwn_pio_txqueue *, uint32_t, const void *, int); 203static void bwn_pio_write_4(struct bwn_mac *, struct bwn_pio_txqueue *, 204 uint16_t, uint32_t); 205static uint16_t bwn_pio_write_multi_2(struct bwn_mac *, 206 struct bwn_pio_txqueue *, uint16_t, const void *, int); 207static uint16_t bwn_pio_write_mbuf_2(struct bwn_mac *, 208 struct bwn_pio_txqueue *, uint16_t, struct mbuf *); 209static struct bwn_pio_txqueue *bwn_pio_parse_cookie(struct bwn_mac *, 210 uint16_t, struct bwn_pio_txpkt **); 211static void bwn_dma_init(struct bwn_mac *); 212static void bwn_dma_rxdirectfifo(struct bwn_mac *, int, uint8_t); 213static int bwn_dma_mask2type(uint64_t); 214static uint64_t bwn_dma_mask(struct bwn_mac *); 215static uint16_t bwn_dma_base(int, int); 216static void bwn_dma_ringfree(struct bwn_dma_ring **); 217static void bwn_dma_32_getdesc(struct bwn_dma_ring *, 218 int, struct bwn_dmadesc_generic **, 219 struct bwn_dmadesc_meta **); 220static void bwn_dma_32_setdesc(struct bwn_dma_ring *, 221 struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int, 222 int, int); 223static void bwn_dma_32_start_transfer(struct bwn_dma_ring *, int); 224static void bwn_dma_32_suspend(struct bwn_dma_ring *); 225static void bwn_dma_32_resume(struct bwn_dma_ring *); 226static int bwn_dma_32_get_curslot(struct bwn_dma_ring *); 227static void bwn_dma_32_set_curslot(struct bwn_dma_ring *, int); 228static void bwn_dma_64_getdesc(struct bwn_dma_ring *, 229 int, struct bwn_dmadesc_generic **, 230 struct bwn_dmadesc_meta **); 231static void bwn_dma_64_setdesc(struct bwn_dma_ring *, 232 struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int, 233 int, int); 234static void bwn_dma_64_start_transfer(struct bwn_dma_ring *, int); 235static void bwn_dma_64_suspend(struct bwn_dma_ring *); 236static void bwn_dma_64_resume(struct bwn_dma_ring *); 237static int bwn_dma_64_get_curslot(struct bwn_dma_ring *); 238static void bwn_dma_64_set_curslot(struct bwn_dma_ring *, int); 239static int bwn_dma_allocringmemory(struct bwn_dma_ring *); 240static void bwn_dma_setup(struct bwn_dma_ring *); 241static void bwn_dma_free_ringmemory(struct bwn_dma_ring *); 242static void bwn_dma_cleanup(struct bwn_dma_ring *); 243static void bwn_dma_free_descbufs(struct bwn_dma_ring *); 244static int bwn_dma_tx_reset(struct bwn_mac *, uint16_t, int); 245static void bwn_dma_rx(struct bwn_dma_ring *); 246static int bwn_dma_rx_reset(struct bwn_mac *, uint16_t, int); 247static void bwn_dma_free_descbuf(struct bwn_dma_ring *, 248 struct bwn_dmadesc_meta *); 249static void bwn_dma_set_redzone(struct bwn_dma_ring *, struct mbuf *); 250static int bwn_dma_gettype(struct bwn_mac *); 251static void bwn_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 252static int bwn_dma_freeslot(struct bwn_dma_ring *); 253static int bwn_dma_nextslot(struct bwn_dma_ring *, int); 254static void bwn_dma_rxeof(struct bwn_dma_ring *, int *); 255static int bwn_dma_newbuf(struct bwn_dma_ring *, 256 struct bwn_dmadesc_generic *, struct bwn_dmadesc_meta *, 257 int); 258static void bwn_dma_buf_addr(void *, bus_dma_segment_t *, int, 259 bus_size_t, int); 260static uint8_t bwn_dma_check_redzone(struct bwn_dma_ring *, struct mbuf *); 261static void bwn_dma_handle_txeof(struct bwn_mac *, 262 const struct bwn_txstatus *); 263static int bwn_dma_tx_start(struct bwn_mac *, struct ieee80211_node *, 264 struct mbuf **); 265static int bwn_dma_getslot(struct bwn_dma_ring *); 266static struct bwn_dma_ring *bwn_dma_select(struct bwn_mac *, 267 uint8_t); 268static int bwn_dma_attach(struct bwn_mac *); 269static struct bwn_dma_ring *bwn_dma_ringsetup(struct bwn_mac *, 270 int, int, int); 271static struct bwn_dma_ring *bwn_dma_parse_cookie(struct bwn_mac *, 272 const struct bwn_txstatus *, uint16_t, int *); 273static void bwn_dma_free(struct bwn_mac *); 274static int bwn_fw_gets(struct bwn_mac *, enum bwn_fwtype); 275static int bwn_fw_get(struct bwn_mac *, enum bwn_fwtype, 276 const char *, struct bwn_fwfile *); 277static void bwn_release_firmware(struct bwn_mac *); 278static void bwn_do_release_fw(struct bwn_fwfile *); 279static uint16_t bwn_fwcaps_read(struct bwn_mac *); 280static int bwn_fwinitvals_write(struct bwn_mac *, 281 const struct bwn_fwinitvals *, size_t, size_t); 282static uint16_t bwn_ant2phy(int); 283static void bwn_mac_write_bssid(struct bwn_mac *); 284static void bwn_mac_setfilter(struct bwn_mac *, uint16_t, 285 const uint8_t *); 286static void bwn_key_dowrite(struct bwn_mac *, uint8_t, uint8_t, 287 const uint8_t *, size_t, const uint8_t *); 288static void bwn_key_macwrite(struct bwn_mac *, uint8_t, 289 const uint8_t *); 290static void bwn_key_write(struct bwn_mac *, uint8_t, uint8_t, 291 const uint8_t *); 292static void bwn_phy_exit(struct bwn_mac *); 293static void bwn_core_stop(struct bwn_mac *); 294static int bwn_switch_band(struct bwn_softc *, 295 struct ieee80211_channel *); 296static void bwn_phy_reset(struct bwn_mac *); 297static int bwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 298static void bwn_set_pretbtt(struct bwn_mac *); 299static int bwn_intr(void *); 300static void bwn_intrtask(void *, int); 301static void bwn_restart(struct bwn_mac *, const char *); 302static void bwn_intr_ucode_debug(struct bwn_mac *); 303static void bwn_intr_tbtt_indication(struct bwn_mac *); 304static void bwn_intr_atim_end(struct bwn_mac *); 305static void bwn_intr_beacon(struct bwn_mac *); 306static void bwn_intr_pmq(struct bwn_mac *); 307static void bwn_intr_noise(struct bwn_mac *); 308static void bwn_intr_txeof(struct bwn_mac *); 309static void bwn_hwreset(void *, int); 310static void bwn_handle_fwpanic(struct bwn_mac *); 311static void bwn_load_beacon0(struct bwn_mac *); 312static void bwn_load_beacon1(struct bwn_mac *); 313static uint32_t bwn_jssi_read(struct bwn_mac *); 314static void bwn_noise_gensample(struct bwn_mac *); 315static void bwn_handle_txeof(struct bwn_mac *, 316 const struct bwn_txstatus *); 317static void bwn_rxeof(struct bwn_mac *, struct mbuf *, const void *); 318static void bwn_phy_txpower_check(struct bwn_mac *, uint32_t); 319static int bwn_tx_start(struct bwn_softc *, struct ieee80211_node *, 320 struct mbuf *); 321static int bwn_tx_isfull(struct bwn_softc *, struct mbuf *); 322static int bwn_set_txhdr(struct bwn_mac *, 323 struct ieee80211_node *, struct mbuf *, struct bwn_txhdr *, 324 uint16_t); 325static void bwn_plcp_genhdr(struct bwn_plcp4 *, const uint16_t, 326 const uint8_t); 327static uint8_t bwn_antenna_sanitize(struct bwn_mac *, uint8_t); 328static uint8_t bwn_get_fbrate(uint8_t); 329static void bwn_txpwr(void *, int); 330static void bwn_tasks(void *); 331static void bwn_task_15s(struct bwn_mac *); 332static void bwn_task_30s(struct bwn_mac *); 333static void bwn_task_60s(struct bwn_mac *); 334static int bwn_plcp_get_ofdmrate(struct bwn_mac *, struct bwn_plcp6 *, 335 uint8_t); 336static int bwn_plcp_get_cckrate(struct bwn_mac *, struct bwn_plcp6 *); 337static void bwn_rx_radiotap(struct bwn_mac *, struct mbuf *, 338 const struct bwn_rxhdr4 *, struct bwn_plcp6 *, int, 339 int, int); 340static void bwn_tsf_read(struct bwn_mac *, uint64_t *); 341static void bwn_set_slot_time(struct bwn_mac *, uint16_t); 342static void bwn_watchdog(void *); 343static void bwn_dma_stop(struct bwn_mac *); 344static void bwn_pio_stop(struct bwn_mac *); 345static void bwn_dma_ringstop(struct bwn_dma_ring **); 346static void bwn_led_attach(struct bwn_mac *); 347static void bwn_led_newstate(struct bwn_mac *, enum ieee80211_state); 348static void bwn_led_event(struct bwn_mac *, int); 349static void bwn_led_blink_start(struct bwn_mac *, int, int); 350static void bwn_led_blink_next(void *); 351static void bwn_led_blink_end(void *); 352static void bwn_rfswitch(void *); 353static void bwn_rf_turnon(struct bwn_mac *); 354static void bwn_rf_turnoff(struct bwn_mac *); 355static void bwn_sysctl_node(struct bwn_softc *); 356 357static struct resource_spec bwn_res_spec_legacy[] = { 358 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 359 { -1, 0, 0 } 360}; 361 362static struct resource_spec bwn_res_spec_msi[] = { 363 { SYS_RES_IRQ, 1, RF_ACTIVE }, 364 { -1, 0, 0 } 365}; 366 367static const struct bwn_channelinfo bwn_chantable_bg = { 368 .channels = { 369 { 2412, 1, 30 }, { 2417, 2, 30 }, { 2422, 3, 30 }, 370 { 2427, 4, 30 }, { 2432, 5, 30 }, { 2437, 6, 30 }, 371 { 2442, 7, 30 }, { 2447, 8, 30 }, { 2452, 9, 30 }, 372 { 2457, 10, 30 }, { 2462, 11, 30 }, { 2467, 12, 30 }, 373 { 2472, 13, 30 }, { 2484, 14, 30 } }, 374 .nchannels = 14 375}; 376 377static const struct bwn_channelinfo bwn_chantable_a = { 378 .channels = { 379 { 5170, 34, 30 }, { 5180, 36, 30 }, { 5190, 38, 30 }, 380 { 5200, 40, 30 }, { 5210, 42, 30 }, { 5220, 44, 30 }, 381 { 5230, 46, 30 }, { 5240, 48, 30 }, { 5260, 52, 30 }, 382 { 5280, 56, 30 }, { 5300, 60, 30 }, { 5320, 64, 30 }, 383 { 5500, 100, 30 }, { 5520, 104, 30 }, { 5540, 108, 30 }, 384 { 5560, 112, 30 }, { 5580, 116, 30 }, { 5600, 120, 30 }, 385 { 5620, 124, 30 }, { 5640, 128, 30 }, { 5660, 132, 30 }, 386 { 5680, 136, 30 }, { 5700, 140, 30 }, { 5745, 149, 30 }, 387 { 5765, 153, 30 }, { 5785, 157, 30 }, { 5805, 161, 30 }, 388 { 5825, 165, 30 }, { 5920, 184, 30 }, { 5940, 188, 30 }, 389 { 5960, 192, 30 }, { 5980, 196, 30 }, { 6000, 200, 30 }, 390 { 6020, 204, 30 }, { 6040, 208, 30 }, { 6060, 212, 30 }, 391 { 6080, 216, 30 } }, 392 .nchannels = 37 393}; 394 395#if 0 396static const struct bwn_channelinfo bwn_chantable_n = { 397 .channels = { 398 { 5160, 32, 30 }, { 5170, 34, 30 }, { 5180, 36, 30 }, 399 { 5190, 38, 30 }, { 5200, 40, 30 }, { 5210, 42, 30 }, 400 { 5220, 44, 30 }, { 5230, 46, 30 }, { 5240, 48, 30 }, 401 { 5250, 50, 30 }, { 5260, 52, 30 }, { 5270, 54, 30 }, 402 { 5280, 56, 30 }, { 5290, 58, 30 }, { 5300, 60, 30 }, 403 { 5310, 62, 30 }, { 5320, 64, 30 }, { 5330, 66, 30 }, 404 { 5340, 68, 30 }, { 5350, 70, 30 }, { 5360, 72, 30 }, 405 { 5370, 74, 30 }, { 5380, 76, 30 }, { 5390, 78, 30 }, 406 { 5400, 80, 30 }, { 5410, 82, 30 }, { 5420, 84, 30 }, 407 { 5430, 86, 30 }, { 5440, 88, 30 }, { 5450, 90, 30 }, 408 { 5460, 92, 30 }, { 5470, 94, 30 }, { 5480, 96, 30 }, 409 { 5490, 98, 30 }, { 5500, 100, 30 }, { 5510, 102, 30 }, 410 { 5520, 104, 30 }, { 5530, 106, 30 }, { 5540, 108, 30 }, 411 { 5550, 110, 30 }, { 5560, 112, 30 }, { 5570, 114, 30 }, 412 { 5580, 116, 30 }, { 5590, 118, 30 }, { 5600, 120, 30 }, 413 { 5610, 122, 30 }, { 5620, 124, 30 }, { 5630, 126, 30 }, 414 { 5640, 128, 30 }, { 5650, 130, 30 }, { 5660, 132, 30 }, 415 { 5670, 134, 30 }, { 5680, 136, 30 }, { 5690, 138, 30 }, 416 { 5700, 140, 30 }, { 5710, 142, 30 }, { 5720, 144, 30 }, 417 { 5725, 145, 30 }, { 5730, 146, 30 }, { 5735, 147, 30 }, 418 { 5740, 148, 30 }, { 5745, 149, 30 }, { 5750, 150, 30 }, 419 { 5755, 151, 30 }, { 5760, 152, 30 }, { 5765, 153, 30 }, 420 { 5770, 154, 30 }, { 5775, 155, 30 }, { 5780, 156, 30 }, 421 { 5785, 157, 30 }, { 5790, 158, 30 }, { 5795, 159, 30 }, 422 { 5800, 160, 30 }, { 5805, 161, 30 }, { 5810, 162, 30 }, 423 { 5815, 163, 30 }, { 5820, 164, 30 }, { 5825, 165, 30 }, 424 { 5830, 166, 30 }, { 5840, 168, 30 }, { 5850, 170, 30 }, 425 { 5860, 172, 30 }, { 5870, 174, 30 }, { 5880, 176, 30 }, 426 { 5890, 178, 30 }, { 5900, 180, 30 }, { 5910, 182, 30 }, 427 { 5920, 184, 30 }, { 5930, 186, 30 }, { 5940, 188, 30 }, 428 { 5950, 190, 30 }, { 5960, 192, 30 }, { 5970, 194, 30 }, 429 { 5980, 196, 30 }, { 5990, 198, 30 }, { 6000, 200, 30 }, 430 { 6010, 202, 30 }, { 6020, 204, 30 }, { 6030, 206, 30 }, 431 { 6040, 208, 30 }, { 6050, 210, 30 }, { 6060, 212, 30 }, 432 { 6070, 214, 30 }, { 6080, 216, 30 }, { 6090, 218, 30 }, 433 { 6100, 220, 30 }, { 6110, 222, 30 }, { 6120, 224, 30 }, 434 { 6130, 226, 30 }, { 6140, 228, 30 } }, 435 .nchannels = 110 436}; 437#endif 438 439#define VENDOR_LED_ACT(vendor) \ 440{ \ 441 .vid = PCI_VENDOR_##vendor, \ 442 .led_act = { BWN_VENDOR_LED_ACT_##vendor } \ 443} 444 445static const struct { 446 uint16_t vid; 447 uint8_t led_act[BWN_LED_MAX]; 448} bwn_vendor_led_act[] = { 449 VENDOR_LED_ACT(COMPAQ), 450 VENDOR_LED_ACT(ASUSTEK) 451}; 452 453static const uint8_t bwn_default_led_act[BWN_LED_MAX] = 454 { BWN_VENDOR_LED_ACT_DEFAULT }; 455 456#undef VENDOR_LED_ACT 457 458static const struct { 459 int on_dur; 460 int off_dur; 461} bwn_led_duration[109] = { 462 [0] = { 400, 100 }, 463 [2] = { 150, 75 }, 464 [4] = { 90, 45 }, 465 [11] = { 66, 34 }, 466 [12] = { 53, 26 }, 467 [18] = { 42, 21 }, 468 [22] = { 35, 17 }, 469 [24] = { 32, 16 }, 470 [36] = { 21, 10 }, 471 [48] = { 16, 8 }, 472 [72] = { 11, 5 }, 473 [96] = { 9, 4 }, 474 [108] = { 7, 3 } 475}; 476 477static const uint16_t bwn_wme_shm_offsets[] = { 478 [0] = BWN_WME_BESTEFFORT, 479 [1] = BWN_WME_BACKGROUND, 480 [2] = BWN_WME_VOICE, 481 [3] = BWN_WME_VIDEO, 482}; 483 484static const struct siba_devid bwn_devs[] = { 485 SIBA_DEV(BROADCOM, 80211, 5, "Revision 5"), 486 SIBA_DEV(BROADCOM, 80211, 6, "Revision 6"), 487 SIBA_DEV(BROADCOM, 80211, 7, "Revision 7"), 488 SIBA_DEV(BROADCOM, 80211, 9, "Revision 9"), 489 SIBA_DEV(BROADCOM, 80211, 10, "Revision 10"), 490 SIBA_DEV(BROADCOM, 80211, 11, "Revision 11"), 491 SIBA_DEV(BROADCOM, 80211, 12, "Revision 12"), 492 SIBA_DEV(BROADCOM, 80211, 13, "Revision 13"), 493 SIBA_DEV(BROADCOM, 80211, 15, "Revision 15"), 494 SIBA_DEV(BROADCOM, 80211, 16, "Revision 16") 495}; 496 497static int 498bwn_probe(device_t dev) 499{ 500 int i; 501 502 for (i = 0; i < nitems(bwn_devs); i++) { 503 if (siba_get_vendor(dev) == bwn_devs[i].sd_vendor && 504 siba_get_device(dev) == bwn_devs[i].sd_device && 505 siba_get_revid(dev) == bwn_devs[i].sd_rev) 506 return (BUS_PROBE_DEFAULT); 507 } 508 509 return (ENXIO); 510} 511 512static int 513bwn_attach(device_t dev) 514{ 515 struct bwn_mac *mac; 516 struct bwn_softc *sc = device_get_softc(dev); 517 int error, i, msic, reg; 518 519 sc->sc_dev = dev; 520#ifdef BWN_DEBUG 521 sc->sc_debug = bwn_debug; 522#endif 523 524 if ((sc->sc_flags & BWN_FLAG_ATTACHED) == 0) { 525 bwn_attach_pre(sc); 526 bwn_sprom_bugfixes(dev); 527 sc->sc_flags |= BWN_FLAG_ATTACHED; 528 } 529 530 if (!TAILQ_EMPTY(&sc->sc_maclist)) { 531 if (siba_get_pci_device(dev) != 0x4313 && 532 siba_get_pci_device(dev) != 0x431a && 533 siba_get_pci_device(dev) != 0x4321) { 534 device_printf(sc->sc_dev, 535 "skip 802.11 cores\n"); 536 return (ENODEV); 537 } 538 } 539 540 mac = malloc(sizeof(*mac), M_DEVBUF, M_WAITOK | M_ZERO); 541 mac->mac_sc = sc; 542 mac->mac_status = BWN_MAC_STATUS_UNINIT; 543 if (bwn_bfp != 0) 544 mac->mac_flags |= BWN_MAC_FLAG_BADFRAME_PREEMP; 545 546 TASK_INIT(&mac->mac_hwreset, 0, bwn_hwreset, mac); 547 TASK_INIT(&mac->mac_intrtask, 0, bwn_intrtask, mac); 548 TASK_INIT(&mac->mac_txpower, 0, bwn_txpwr, mac); 549 550 error = bwn_attach_core(mac); 551 if (error) 552 goto fail0; 553 bwn_led_attach(mac); 554 555 device_printf(sc->sc_dev, "WLAN (chipid %#x rev %u) " 556 "PHY (analog %d type %d rev %d) RADIO (manuf %#x ver %#x rev %d)\n", 557 siba_get_chipid(sc->sc_dev), siba_get_revid(sc->sc_dev), 558 mac->mac_phy.analog, mac->mac_phy.type, mac->mac_phy.rev, 559 mac->mac_phy.rf_manuf, mac->mac_phy.rf_ver, 560 mac->mac_phy.rf_rev); 561 if (mac->mac_flags & BWN_MAC_FLAG_DMA) 562 device_printf(sc->sc_dev, "DMA (%d bits)\n", 563 mac->mac_method.dma.dmatype); 564 else 565 device_printf(sc->sc_dev, "PIO\n"); 566 567#ifdef BWN_GPL_PHY 568 device_printf(sc->sc_dev, 569 "Note: compiled with BWN_GPL_PHY; includes GPLv2 code\n"); 570#endif 571 572 /* 573 * setup PCI resources and interrupt. 574 */ 575 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 576 msic = pci_msi_count(dev); 577 if (bootverbose) 578 device_printf(sc->sc_dev, "MSI count : %d\n", msic); 579 } else 580 msic = 0; 581 582 mac->mac_intr_spec = bwn_res_spec_legacy; 583 if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0) { 584 if (pci_alloc_msi(dev, &msic) == 0) { 585 device_printf(sc->sc_dev, 586 "Using %d MSI messages\n", msic); 587 mac->mac_intr_spec = bwn_res_spec_msi; 588 mac->mac_msi = 1; 589 } 590 } 591 592 error = bus_alloc_resources(dev, mac->mac_intr_spec, 593 mac->mac_res_irq); 594 if (error) { 595 device_printf(sc->sc_dev, 596 "couldn't allocate IRQ resources (%d)\n", error); 597 goto fail1; 598 } 599 600 if (mac->mac_msi == 0) 601 error = bus_setup_intr(dev, mac->mac_res_irq[0], 602 INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac, 603 &mac->mac_intrhand[0]); 604 else { 605 for (i = 0; i < BWN_MSI_MESSAGES; i++) { 606 error = bus_setup_intr(dev, mac->mac_res_irq[i], 607 INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac, 608 &mac->mac_intrhand[i]); 609 if (error != 0) { 610 device_printf(sc->sc_dev, 611 "couldn't setup interrupt (%d)\n", error); 612 break; 613 } 614 } 615 } 616 617 TAILQ_INSERT_TAIL(&sc->sc_maclist, mac, mac_list); 618 619 /* 620 * calls attach-post routine 621 */ 622 if ((sc->sc_flags & BWN_FLAG_ATTACHED) != 0) 623 bwn_attach_post(sc); 624 625 return (0); 626fail1: 627 if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0) 628 pci_release_msi(dev); 629fail0: 630 free(mac, M_DEVBUF); 631 return (error); 632} 633 634static int 635bwn_is_valid_ether_addr(uint8_t *addr) 636{ 637 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 638 639 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) 640 return (FALSE); 641 642 return (TRUE); 643} 644 645static int 646bwn_attach_post(struct bwn_softc *sc) 647{ 648 struct ieee80211com *ic = &sc->sc_ic; 649 650 ic->ic_softc = sc; 651 ic->ic_name = device_get_nameunit(sc->sc_dev); 652 /* XXX not right but it's not used anywhere important */ 653 ic->ic_phytype = IEEE80211_T_OFDM; 654 ic->ic_opmode = IEEE80211_M_STA; 655 ic->ic_caps = 656 IEEE80211_C_STA /* station mode supported */ 657 | IEEE80211_C_MONITOR /* monitor mode */ 658 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 659 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 660 | IEEE80211_C_SHSLOT /* short slot time supported */ 661 | IEEE80211_C_WME /* WME/WMM supported */ 662 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 663#if 0 664 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 665#endif 666 | IEEE80211_C_TXPMGT /* capable of txpow mgt */ 667 ; 668 669 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; /* s/w bmiss */ 670 671 IEEE80211_ADDR_COPY(ic->ic_macaddr, 672 bwn_is_valid_ether_addr(siba_sprom_get_mac_80211a(sc->sc_dev)) ? 673 siba_sprom_get_mac_80211a(sc->sc_dev) : 674 siba_sprom_get_mac_80211bg(sc->sc_dev)); 675 676 /* call MI attach routine. */ 677 ieee80211_ifattach(ic); 678 679 ic->ic_headroom = sizeof(struct bwn_txhdr); 680 681 /* override default methods */ 682 ic->ic_raw_xmit = bwn_raw_xmit; 683 ic->ic_updateslot = bwn_updateslot; 684 ic->ic_update_promisc = bwn_update_promisc; 685 ic->ic_wme.wme_update = bwn_wme_update; 686 ic->ic_scan_start = bwn_scan_start; 687 ic->ic_scan_end = bwn_scan_end; 688 ic->ic_set_channel = bwn_set_channel; 689 ic->ic_vap_create = bwn_vap_create; 690 ic->ic_vap_delete = bwn_vap_delete; 691 ic->ic_transmit = bwn_transmit; 692 ic->ic_parent = bwn_parent; 693 694 ieee80211_radiotap_attach(ic, 695 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 696 BWN_TX_RADIOTAP_PRESENT, 697 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 698 BWN_RX_RADIOTAP_PRESENT); 699 700 bwn_sysctl_node(sc); 701 702 if (bootverbose) 703 ieee80211_announce(ic); 704 return (0); 705} 706 707static void 708bwn_phy_detach(struct bwn_mac *mac) 709{ 710 711 if (mac->mac_phy.detach != NULL) 712 mac->mac_phy.detach(mac); 713} 714 715static int 716bwn_detach(device_t dev) 717{ 718 struct bwn_softc *sc = device_get_softc(dev); 719 struct bwn_mac *mac = sc->sc_curmac; 720 struct ieee80211com *ic = &sc->sc_ic; 721 int i; 722 723 sc->sc_flags |= BWN_FLAG_INVALID; 724 725 if (device_is_attached(sc->sc_dev)) { 726 BWN_LOCK(sc); 727 bwn_stop(sc); 728 BWN_UNLOCK(sc); 729 bwn_dma_free(mac); 730 callout_drain(&sc->sc_led_blink_ch); 731 callout_drain(&sc->sc_rfswitch_ch); 732 callout_drain(&sc->sc_task_ch); 733 callout_drain(&sc->sc_watchdog_ch); 734 bwn_phy_detach(mac); 735 ieee80211_draintask(ic, &mac->mac_hwreset); 736 ieee80211_draintask(ic, &mac->mac_txpower); 737 ieee80211_ifdetach(ic); 738 } 739 taskqueue_drain(sc->sc_tq, &mac->mac_intrtask); 740 taskqueue_free(sc->sc_tq); 741 742 for (i = 0; i < BWN_MSI_MESSAGES; i++) { 743 if (mac->mac_intrhand[i] != NULL) { 744 bus_teardown_intr(dev, mac->mac_res_irq[i], 745 mac->mac_intrhand[i]); 746 mac->mac_intrhand[i] = NULL; 747 } 748 } 749 bus_release_resources(dev, mac->mac_intr_spec, mac->mac_res_irq); 750 if (mac->mac_msi != 0) 751 pci_release_msi(dev); 752 mbufq_drain(&sc->sc_snd); 753 bwn_release_firmware(mac); 754 BWN_LOCK_DESTROY(sc); 755 return (0); 756} 757 758static void 759bwn_attach_pre(struct bwn_softc *sc) 760{ 761 762 BWN_LOCK_INIT(sc); 763 TAILQ_INIT(&sc->sc_maclist); 764 callout_init_mtx(&sc->sc_rfswitch_ch, &sc->sc_mtx, 0); 765 callout_init_mtx(&sc->sc_task_ch, &sc->sc_mtx, 0); 766 callout_init_mtx(&sc->sc_watchdog_ch, &sc->sc_mtx, 0); 767 mbufq_init(&sc->sc_snd, ifqmaxlen); 768 sc->sc_tq = taskqueue_create_fast("bwn_taskq", M_NOWAIT, 769 taskqueue_thread_enqueue, &sc->sc_tq); 770 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 771 "%s taskq", device_get_nameunit(sc->sc_dev)); 772} 773 774static void 775bwn_sprom_bugfixes(device_t dev) 776{ 777#define BWN_ISDEV(_vendor, _device, _subvendor, _subdevice) \ 778 ((siba_get_pci_vendor(dev) == PCI_VENDOR_##_vendor) && \ 779 (siba_get_pci_device(dev) == _device) && \ 780 (siba_get_pci_subvendor(dev) == PCI_VENDOR_##_subvendor) && \ 781 (siba_get_pci_subdevice(dev) == _subdevice)) 782 783 if (siba_get_pci_subvendor(dev) == PCI_VENDOR_APPLE && 784 siba_get_pci_subdevice(dev) == 0x4e && 785 siba_get_pci_revid(dev) > 0x40) 786 siba_sprom_set_bf_lo(dev, 787 siba_sprom_get_bf_lo(dev) | BWN_BFL_PACTRL); 788 if (siba_get_pci_subvendor(dev) == SIBA_BOARDVENDOR_DELL && 789 siba_get_chipid(dev) == 0x4301 && siba_get_pci_revid(dev) == 0x74) 790 siba_sprom_set_bf_lo(dev, 791 siba_sprom_get_bf_lo(dev) | BWN_BFL_BTCOEXIST); 792 if (siba_get_type(dev) == SIBA_TYPE_PCI) { 793 if (BWN_ISDEV(BROADCOM, 0x4318, ASUSTEK, 0x100f) || 794 BWN_ISDEV(BROADCOM, 0x4320, DELL, 0x0003) || 795 BWN_ISDEV(BROADCOM, 0x4320, HP, 0x12f8) || 796 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0013) || 797 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0014) || 798 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0015) || 799 BWN_ISDEV(BROADCOM, 0x4320, MOTOROLA, 0x7010)) 800 siba_sprom_set_bf_lo(dev, 801 siba_sprom_get_bf_lo(dev) & ~BWN_BFL_BTCOEXIST); 802 } 803#undef BWN_ISDEV 804} 805 806static void 807bwn_parent(struct ieee80211com *ic) 808{ 809 struct bwn_softc *sc = ic->ic_softc; 810 int startall = 0; 811 812 BWN_LOCK(sc); 813 if (ic->ic_nrunning > 0) { 814 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) { 815 bwn_init(sc); 816 startall = 1; 817 } else 818 bwn_update_promisc(ic); 819 } else if (sc->sc_flags & BWN_FLAG_RUNNING) 820 bwn_stop(sc); 821 BWN_UNLOCK(sc); 822 823 if (startall) 824 ieee80211_start_all(ic); 825} 826 827static int 828bwn_transmit(struct ieee80211com *ic, struct mbuf *m) 829{ 830 struct bwn_softc *sc = ic->ic_softc; 831 int error; 832 833 BWN_LOCK(sc); 834 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) { 835 BWN_UNLOCK(sc); 836 return (ENXIO); 837 } 838 error = mbufq_enqueue(&sc->sc_snd, m); 839 if (error) { 840 BWN_UNLOCK(sc); 841 return (error); 842 } 843 bwn_start(sc); 844 BWN_UNLOCK(sc); 845 return (0); 846} 847 848static void 849bwn_start(struct bwn_softc *sc) 850{ 851 struct bwn_mac *mac = sc->sc_curmac; 852 struct ieee80211_frame *wh; 853 struct ieee80211_node *ni; 854 struct ieee80211_key *k; 855 struct mbuf *m; 856 857 BWN_ASSERT_LOCKED(sc); 858 859 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 || mac == NULL || 860 mac->mac_status < BWN_MAC_STATUS_STARTED) 861 return; 862 863 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 864 if (bwn_tx_isfull(sc, m)) 865 break; 866 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 867 if (ni == NULL) { 868 device_printf(sc->sc_dev, "unexpected NULL ni\n"); 869 m_freem(m); 870 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 871 continue; 872 } 873 wh = mtod(m, struct ieee80211_frame *); 874 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 875 k = ieee80211_crypto_encap(ni, m); 876 if (k == NULL) { 877 if_inc_counter(ni->ni_vap->iv_ifp, 878 IFCOUNTER_OERRORS, 1); 879 ieee80211_free_node(ni); 880 m_freem(m); 881 continue; 882 } 883 } 884 wh = NULL; /* Catch any invalid use */ 885 if (bwn_tx_start(sc, ni, m) != 0) { 886 if (ni != NULL) { 887 if_inc_counter(ni->ni_vap->iv_ifp, 888 IFCOUNTER_OERRORS, 1); 889 ieee80211_free_node(ni); 890 } 891 continue; 892 } 893 sc->sc_watchdog_timer = 5; 894 } 895} 896 897static int 898bwn_tx_isfull(struct bwn_softc *sc, struct mbuf *m) 899{ 900 struct bwn_dma_ring *dr; 901 struct bwn_mac *mac = sc->sc_curmac; 902 struct bwn_pio_txqueue *tq; 903 int pktlen = roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4); 904 905 BWN_ASSERT_LOCKED(sc); 906 907 if (mac->mac_flags & BWN_MAC_FLAG_DMA) { 908 dr = bwn_dma_select(mac, M_WME_GETAC(m)); 909 if (dr->dr_stop == 1 || 910 bwn_dma_freeslot(dr) < BWN_TX_SLOTS_PER_FRAME) { 911 dr->dr_stop = 1; 912 goto full; 913 } 914 } else { 915 tq = bwn_pio_select(mac, M_WME_GETAC(m)); 916 if (tq->tq_free == 0 || pktlen > tq->tq_size || 917 pktlen > (tq->tq_size - tq->tq_used)) 918 goto full; 919 } 920 return (0); 921full: 922 mbufq_prepend(&sc->sc_snd, m); 923 return (1); 924} 925 926static int 927bwn_tx_start(struct bwn_softc *sc, struct ieee80211_node *ni, struct mbuf *m) 928{ 929 struct bwn_mac *mac = sc->sc_curmac; 930 int error; 931 932 BWN_ASSERT_LOCKED(sc); 933 934 if (m->m_pkthdr.len < IEEE80211_MIN_LEN || mac == NULL) { 935 m_freem(m); 936 return (ENXIO); 937 } 938 939 error = (mac->mac_flags & BWN_MAC_FLAG_DMA) ? 940 bwn_dma_tx_start(mac, ni, &m) : bwn_pio_tx_start(mac, ni, &m); 941 if (error) { 942 m_freem(m); 943 return (error); 944 } 945 return (0); 946} 947 948static int 949bwn_pio_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, 950 struct mbuf **mp) 951{ 952 struct bwn_pio_txpkt *tp; 953 struct bwn_pio_txqueue *tq; 954 struct bwn_softc *sc = mac->mac_sc; 955 struct bwn_txhdr txhdr; 956 struct mbuf *m, *m_new; 957 uint32_t ctl32; 958 int error; 959 uint16_t ctl16; 960 961 BWN_ASSERT_LOCKED(sc); 962 963 /* XXX TODO send packets after DTIM */ 964 965 m = *mp; 966 tq = bwn_pio_select(mac, M_WME_GETAC(m)); 967 KASSERT(!TAILQ_EMPTY(&tq->tq_pktlist), ("%s: fail", __func__)); 968 tp = TAILQ_FIRST(&tq->tq_pktlist); 969 tp->tp_ni = ni; 970 tp->tp_m = m; 971 972 error = bwn_set_txhdr(mac, ni, m, &txhdr, BWN_PIO_COOKIE(tq, tp)); 973 if (error) { 974 device_printf(sc->sc_dev, "tx fail\n"); 975 return (error); 976 } 977 978 TAILQ_REMOVE(&tq->tq_pktlist, tp, tp_list); 979 tq->tq_used += roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4); 980 tq->tq_free--; 981 982 if (siba_get_revid(sc->sc_dev) >= 8) { 983 /* 984 * XXX please removes m_defrag(9) 985 */ 986 m_new = m_defrag(*mp, M_NOWAIT); 987 if (m_new == NULL) { 988 device_printf(sc->sc_dev, 989 "%s: can't defrag TX buffer\n", 990 __func__); 991 return (ENOBUFS); 992 } 993 *mp = m_new; 994 if (m_new->m_next != NULL) 995 device_printf(sc->sc_dev, 996 "TODO: fragmented packets for PIO\n"); 997 tp->tp_m = m_new; 998 999 /* send HEADER */ 1000 ctl32 = bwn_pio_write_multi_4(mac, tq, 1001 (BWN_PIO_READ_4(mac, tq, BWN_PIO8_TXCTL) | 1002 BWN_PIO8_TXCTL_FRAMEREADY) & ~BWN_PIO8_TXCTL_EOF, 1003 (const uint8_t *)&txhdr, BWN_HDRSIZE(mac)); 1004 /* send BODY */ 1005 ctl32 = bwn_pio_write_multi_4(mac, tq, ctl32, 1006 mtod(m_new, const void *), m_new->m_pkthdr.len); 1007 bwn_pio_write_4(mac, tq, BWN_PIO_TXCTL, 1008 ctl32 | BWN_PIO8_TXCTL_EOF); 1009 } else { 1010 ctl16 = bwn_pio_write_multi_2(mac, tq, 1011 (bwn_pio_read_2(mac, tq, BWN_PIO_TXCTL) | 1012 BWN_PIO_TXCTL_FRAMEREADY) & ~BWN_PIO_TXCTL_EOF, 1013 (const uint8_t *)&txhdr, BWN_HDRSIZE(mac)); 1014 ctl16 = bwn_pio_write_mbuf_2(mac, tq, ctl16, m); 1015 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, 1016 ctl16 | BWN_PIO_TXCTL_EOF); 1017 } 1018 1019 return (0); 1020} 1021 1022static struct bwn_pio_txqueue * 1023bwn_pio_select(struct bwn_mac *mac, uint8_t prio) 1024{ 1025 1026 if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0) 1027 return (&mac->mac_method.pio.wme[WME_AC_BE]); 1028 1029 switch (prio) { 1030 case 0: 1031 return (&mac->mac_method.pio.wme[WME_AC_BE]); 1032 case 1: 1033 return (&mac->mac_method.pio.wme[WME_AC_BK]); 1034 case 2: 1035 return (&mac->mac_method.pio.wme[WME_AC_VI]); 1036 case 3: 1037 return (&mac->mac_method.pio.wme[WME_AC_VO]); 1038 } 1039 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 1040 return (NULL); 1041} 1042 1043static int 1044bwn_dma_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, 1045 struct mbuf **mp) 1046{ 1047#define BWN_GET_TXHDRCACHE(slot) \ 1048 &(txhdr_cache[(slot / BWN_TX_SLOTS_PER_FRAME) * BWN_HDRSIZE(mac)]) 1049 struct bwn_dma *dma = &mac->mac_method.dma; 1050 struct bwn_dma_ring *dr = bwn_dma_select(mac, M_WME_GETAC(*mp)); 1051 struct bwn_dmadesc_generic *desc; 1052 struct bwn_dmadesc_meta *mt; 1053 struct bwn_softc *sc = mac->mac_sc; 1054 struct mbuf *m; 1055 uint8_t *txhdr_cache = (uint8_t *)dr->dr_txhdr_cache; 1056 int error, slot, backup[2] = { dr->dr_curslot, dr->dr_usedslot }; 1057 1058 BWN_ASSERT_LOCKED(sc); 1059 KASSERT(!dr->dr_stop, ("%s:%d: fail", __func__, __LINE__)); 1060 1061 /* XXX send after DTIM */ 1062 1063 m = *mp; 1064 slot = bwn_dma_getslot(dr); 1065 dr->getdesc(dr, slot, &desc, &mt); 1066 KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_HEADER, 1067 ("%s:%d: fail", __func__, __LINE__)); 1068 1069 error = bwn_set_txhdr(dr->dr_mac, ni, m, 1070 (struct bwn_txhdr *)BWN_GET_TXHDRCACHE(slot), 1071 BWN_DMA_COOKIE(dr, slot)); 1072 if (error) 1073 goto fail; 1074 error = bus_dmamap_load(dr->dr_txring_dtag, mt->mt_dmap, 1075 BWN_GET_TXHDRCACHE(slot), BWN_HDRSIZE(mac), bwn_dma_ring_addr, 1076 &mt->mt_paddr, BUS_DMA_NOWAIT); 1077 if (error) { 1078 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 1079 __func__, error); 1080 goto fail; 1081 } 1082 bus_dmamap_sync(dr->dr_txring_dtag, mt->mt_dmap, 1083 BUS_DMASYNC_PREWRITE); 1084 dr->setdesc(dr, desc, mt->mt_paddr, BWN_HDRSIZE(mac), 1, 0, 0); 1085 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 1086 BUS_DMASYNC_PREWRITE); 1087 1088 slot = bwn_dma_getslot(dr); 1089 dr->getdesc(dr, slot, &desc, &mt); 1090 KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_BODY && 1091 mt->mt_islast == 1, ("%s:%d: fail", __func__, __LINE__)); 1092 mt->mt_m = m; 1093 mt->mt_ni = ni; 1094 1095 error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap, m, 1096 bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT); 1097 if (error && error != EFBIG) { 1098 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 1099 __func__, error); 1100 goto fail; 1101 } 1102 if (error) { /* error == EFBIG */ 1103 struct mbuf *m_new; 1104 1105 m_new = m_defrag(m, M_NOWAIT); 1106 if (m_new == NULL) { 1107 device_printf(sc->sc_dev, 1108 "%s: can't defrag TX buffer\n", 1109 __func__); 1110 error = ENOBUFS; 1111 goto fail; 1112 } 1113 *mp = m = m_new; 1114 1115 mt->mt_m = m; 1116 error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap, 1117 m, bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT); 1118 if (error) { 1119 device_printf(sc->sc_dev, 1120 "%s: can't load TX buffer (2) %d\n", 1121 __func__, error); 1122 goto fail; 1123 } 1124 } 1125 bus_dmamap_sync(dma->txbuf_dtag, mt->mt_dmap, BUS_DMASYNC_PREWRITE); 1126 dr->setdesc(dr, desc, mt->mt_paddr, m->m_pkthdr.len, 0, 1, 1); 1127 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 1128 BUS_DMASYNC_PREWRITE); 1129 1130 /* XXX send after DTIM */ 1131 1132 dr->start_transfer(dr, bwn_dma_nextslot(dr, slot)); 1133 return (0); 1134fail: 1135 dr->dr_curslot = backup[0]; 1136 dr->dr_usedslot = backup[1]; 1137 return (error); 1138#undef BWN_GET_TXHDRCACHE 1139} 1140 1141static void 1142bwn_watchdog(void *arg) 1143{ 1144 struct bwn_softc *sc = arg; 1145 1146 if (sc->sc_watchdog_timer != 0 && --sc->sc_watchdog_timer == 0) { 1147 device_printf(sc->sc_dev, "device timeout\n"); 1148 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1149 } 1150 callout_schedule(&sc->sc_watchdog_ch, hz); 1151} 1152 1153static int 1154bwn_attach_core(struct bwn_mac *mac) 1155{ 1156 struct bwn_softc *sc = mac->mac_sc; 1157 int error, have_bg = 0, have_a = 0; 1158 1159 KASSERT(siba_get_revid(sc->sc_dev) >= 5, 1160 ("unsupported revision %d", siba_get_revid(sc->sc_dev))); 1161 1162 if (bwn_is_bus_siba(mac)) { 1163 uint32_t high; 1164 1165 siba_powerup(sc->sc_dev, 0); 1166 high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH); 1167 have_a = (high & BWN_TGSHIGH_HAVE_5GHZ) ? 1 : 0; 1168 have_bg = (high & BWN_TGSHIGH_HAVE_2GHZ) ? 1 : 0; 1169 if (high & BWN_TGSHIGH_DUALPHY) { 1170 have_bg = 1; 1171 have_a = 1; 1172 } 1173#if 0 1174 device_printf(sc->sc_dev, "%s: high=0x%08x, have_a=%d, have_bg=%d," 1175 " deviceid=0x%04x, siba_deviceid=0x%04x\n", 1176 __func__, 1177 high, 1178 have_a, 1179 have_bg, 1180 siba_get_pci_device(sc->sc_dev), 1181 siba_get_chipid(sc->sc_dev)); 1182#endif 1183 } else { 1184 device_printf(sc->sc_dev, "%s: not siba; bailing\n", __func__); 1185 error = ENXIO; 1186 goto fail; 1187 } 1188 1189 /* 1190 * Guess at whether it has A-PHY or G-PHY. 1191 * This is just used for resetting the core to probe things; 1192 * we will re-guess once it's all up and working. 1193 */ 1194 bwn_reset_core(mac, have_bg); 1195 1196 /* 1197 * Get the PHY version. 1198 */ 1199 error = bwn_phy_getinfo(mac, have_bg); 1200 if (error) 1201 goto fail; 1202 1203 /* 1204 * This is the whitelist of devices which we "believe" 1205 * the SPROM PHY config from. The rest are "guessed". 1206 */ 1207 if (siba_get_pci_device(sc->sc_dev) != 0x4312 && 1208 siba_get_pci_device(sc->sc_dev) != 0x4315 && 1209 siba_get_pci_device(sc->sc_dev) != 0x4319 && 1210 siba_get_pci_device(sc->sc_dev) != 0x4324 && 1211 siba_get_pci_device(sc->sc_dev) != 0x4328 && 1212 siba_get_pci_device(sc->sc_dev) != 0x432b) { 1213 have_a = have_bg = 0; 1214 if (mac->mac_phy.type == BWN_PHYTYPE_A) 1215 have_a = 1; 1216 else if (mac->mac_phy.type == BWN_PHYTYPE_G || 1217 mac->mac_phy.type == BWN_PHYTYPE_N || 1218 mac->mac_phy.type == BWN_PHYTYPE_LP) 1219 have_bg = 1; 1220 else 1221 KASSERT(0 == 1, ("%s: unknown phy type (%d)", __func__, 1222 mac->mac_phy.type)); 1223 } 1224 1225 /* 1226 * XXX The PHY-G support doesn't do 5GHz operation. 1227 */ 1228 if (mac->mac_phy.type != BWN_PHYTYPE_LP && 1229 mac->mac_phy.type != BWN_PHYTYPE_N) { 1230 device_printf(sc->sc_dev, 1231 "%s: forcing 2GHz only; no dual-band support for PHY\n", 1232 __func__); 1233 have_a = 0; 1234 have_bg = 1; 1235 } 1236 1237 mac->mac_phy.phy_n = NULL; 1238 1239 if (mac->mac_phy.type == BWN_PHYTYPE_G) { 1240 mac->mac_phy.attach = bwn_phy_g_attach; 1241 mac->mac_phy.detach = bwn_phy_g_detach; 1242 mac->mac_phy.prepare_hw = bwn_phy_g_prepare_hw; 1243 mac->mac_phy.init_pre = bwn_phy_g_init_pre; 1244 mac->mac_phy.init = bwn_phy_g_init; 1245 mac->mac_phy.exit = bwn_phy_g_exit; 1246 mac->mac_phy.phy_read = bwn_phy_g_read; 1247 mac->mac_phy.phy_write = bwn_phy_g_write; 1248 mac->mac_phy.rf_read = bwn_phy_g_rf_read; 1249 mac->mac_phy.rf_write = bwn_phy_g_rf_write; 1250 mac->mac_phy.use_hwpctl = bwn_phy_g_hwpctl; 1251 mac->mac_phy.rf_onoff = bwn_phy_g_rf_onoff; 1252 mac->mac_phy.switch_analog = bwn_phy_switch_analog; 1253 mac->mac_phy.switch_channel = bwn_phy_g_switch_channel; 1254 mac->mac_phy.get_default_chan = bwn_phy_g_get_default_chan; 1255 mac->mac_phy.set_antenna = bwn_phy_g_set_antenna; 1256 mac->mac_phy.set_im = bwn_phy_g_im; 1257 mac->mac_phy.recalc_txpwr = bwn_phy_g_recalc_txpwr; 1258 mac->mac_phy.set_txpwr = bwn_phy_g_set_txpwr; 1259 mac->mac_phy.task_15s = bwn_phy_g_task_15s; 1260 mac->mac_phy.task_60s = bwn_phy_g_task_60s; 1261 } else if (mac->mac_phy.type == BWN_PHYTYPE_LP) { 1262 mac->mac_phy.init_pre = bwn_phy_lp_init_pre; 1263 mac->mac_phy.init = bwn_phy_lp_init; 1264 mac->mac_phy.phy_read = bwn_phy_lp_read; 1265 mac->mac_phy.phy_write = bwn_phy_lp_write; 1266 mac->mac_phy.phy_maskset = bwn_phy_lp_maskset; 1267 mac->mac_phy.rf_read = bwn_phy_lp_rf_read; 1268 mac->mac_phy.rf_write = bwn_phy_lp_rf_write; 1269 mac->mac_phy.rf_onoff = bwn_phy_lp_rf_onoff; 1270 mac->mac_phy.switch_analog = bwn_phy_lp_switch_analog; 1271 mac->mac_phy.switch_channel = bwn_phy_lp_switch_channel; 1272 mac->mac_phy.get_default_chan = bwn_phy_lp_get_default_chan; 1273 mac->mac_phy.set_antenna = bwn_phy_lp_set_antenna; 1274 mac->mac_phy.task_60s = bwn_phy_lp_task_60s; 1275 } else if (mac->mac_phy.type == BWN_PHYTYPE_N) { 1276 mac->mac_phy.attach = bwn_phy_n_attach; 1277 mac->mac_phy.detach = bwn_phy_n_detach; 1278 mac->mac_phy.prepare_hw = bwn_phy_n_prepare_hw; 1279 mac->mac_phy.init_pre = bwn_phy_n_init_pre; 1280 mac->mac_phy.init = bwn_phy_n_init; 1281 mac->mac_phy.exit = bwn_phy_n_exit; 1282 mac->mac_phy.phy_read = bwn_phy_n_read; 1283 mac->mac_phy.phy_write = bwn_phy_n_write; 1284 mac->mac_phy.rf_read = bwn_phy_n_rf_read; 1285 mac->mac_phy.rf_write = bwn_phy_n_rf_write; 1286 mac->mac_phy.use_hwpctl = bwn_phy_n_hwpctl; 1287 mac->mac_phy.rf_onoff = bwn_phy_n_rf_onoff; 1288 mac->mac_phy.switch_analog = bwn_phy_n_switch_analog; 1289 mac->mac_phy.switch_channel = bwn_phy_n_switch_channel; 1290 mac->mac_phy.get_default_chan = bwn_phy_n_get_default_chan; 1291 mac->mac_phy.set_antenna = bwn_phy_n_set_antenna; 1292 mac->mac_phy.set_im = bwn_phy_n_im; 1293 mac->mac_phy.recalc_txpwr = bwn_phy_n_recalc_txpwr; 1294 mac->mac_phy.set_txpwr = bwn_phy_n_set_txpwr; 1295 mac->mac_phy.task_15s = bwn_phy_n_task_15s; 1296 mac->mac_phy.task_60s = bwn_phy_n_task_60s; 1297 } else { 1298 device_printf(sc->sc_dev, "unsupported PHY type (%d)\n", 1299 mac->mac_phy.type); 1300 error = ENXIO; 1301 goto fail; 1302 } 1303 1304 mac->mac_phy.gmode = have_bg; 1305 if (mac->mac_phy.attach != NULL) { 1306 error = mac->mac_phy.attach(mac); 1307 if (error) { 1308 device_printf(sc->sc_dev, "failed\n"); 1309 goto fail; 1310 } 1311 } 1312 1313 bwn_reset_core(mac, have_bg); 1314 1315 error = bwn_chiptest(mac); 1316 if (error) 1317 goto fail; 1318 error = bwn_setup_channels(mac, have_bg, have_a); 1319 if (error) { 1320 device_printf(sc->sc_dev, "failed to setup channels\n"); 1321 goto fail; 1322 } 1323 1324 if (sc->sc_curmac == NULL) 1325 sc->sc_curmac = mac; 1326 1327 error = bwn_dma_attach(mac); 1328 if (error != 0) { 1329 device_printf(sc->sc_dev, "failed to initialize DMA\n"); 1330 goto fail; 1331 } 1332 1333 mac->mac_phy.switch_analog(mac, 0); 1334 1335 siba_dev_down(sc->sc_dev, 0); 1336fail: 1337 siba_powerdown(sc->sc_dev); 1338 bwn_release_firmware(mac); 1339 return (error); 1340} 1341 1342/* 1343 * Reset - SIBA. 1344 * 1345 * XXX TODO: implement BCMA version! 1346 */ 1347void 1348bwn_reset_core(struct bwn_mac *mac, int g_mode) 1349{ 1350 struct bwn_softc *sc = mac->mac_sc; 1351 uint32_t low, ctl; 1352 uint32_t flags = 0; 1353 1354 DPRINTF(sc, BWN_DEBUG_RESET, "%s: g_mode=%d\n", __func__, g_mode); 1355 1356 flags |= (BWN_TGSLOW_PHYCLOCK_ENABLE | BWN_TGSLOW_PHYRESET); 1357 if (g_mode) 1358 flags |= BWN_TGSLOW_SUPPORT_G; 1359 1360 /* XXX N-PHY only; and hard-code to 20MHz for now */ 1361 if (mac->mac_phy.type == BWN_PHYTYPE_N) 1362 flags |= BWN_TGSLOW_PHY_BANDWIDTH_20MHZ; 1363 1364 siba_dev_up(sc->sc_dev, flags); 1365 DELAY(2000); 1366 1367 /* Take PHY out of reset */ 1368 low = (siba_read_4(sc->sc_dev, SIBA_TGSLOW) | SIBA_TGSLOW_FGC) & 1369 ~(BWN_TGSLOW_PHYRESET | BWN_TGSLOW_PHYCLOCK_ENABLE); 1370 siba_write_4(sc->sc_dev, SIBA_TGSLOW, low); 1371 siba_read_4(sc->sc_dev, SIBA_TGSLOW); 1372 DELAY(2000); 1373 low &= ~SIBA_TGSLOW_FGC; 1374 low |= BWN_TGSLOW_PHYCLOCK_ENABLE; 1375 siba_write_4(sc->sc_dev, SIBA_TGSLOW, low); 1376 siba_read_4(sc->sc_dev, SIBA_TGSLOW); 1377 DELAY(2000); 1378 1379 if (mac->mac_phy.switch_analog != NULL) 1380 mac->mac_phy.switch_analog(mac, 1); 1381 1382 ctl = BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GMODE; 1383 if (g_mode) 1384 ctl |= BWN_MACCTL_GMODE; 1385 BWN_WRITE_4(mac, BWN_MACCTL, ctl | BWN_MACCTL_IHR_ON); 1386} 1387 1388static int 1389bwn_phy_getinfo(struct bwn_mac *mac, int gmode) 1390{ 1391 struct bwn_phy *phy = &mac->mac_phy; 1392 struct bwn_softc *sc = mac->mac_sc; 1393 uint32_t tmp; 1394 1395 /* PHY */ 1396 tmp = BWN_READ_2(mac, BWN_PHYVER); 1397 phy->gmode = gmode; 1398 phy->rf_on = 1; 1399 phy->analog = (tmp & BWN_PHYVER_ANALOG) >> 12; 1400 phy->type = (tmp & BWN_PHYVER_TYPE) >> 8; 1401 phy->rev = (tmp & BWN_PHYVER_VERSION); 1402 if ((phy->type == BWN_PHYTYPE_A && phy->rev >= 4) || 1403 (phy->type == BWN_PHYTYPE_B && phy->rev != 2 && 1404 phy->rev != 4 && phy->rev != 6 && phy->rev != 7) || 1405 (phy->type == BWN_PHYTYPE_G && phy->rev > 9) || 1406 (phy->type == BWN_PHYTYPE_N && phy->rev > 4) || 1407 (phy->type == BWN_PHYTYPE_LP && phy->rev > 2)) 1408 goto unsupphy; 1409 1410 /* RADIO */ 1411 if (siba_get_chipid(sc->sc_dev) == 0x4317) { 1412 if (siba_get_chiprev(sc->sc_dev) == 0) 1413 tmp = 0x3205017f; 1414 else if (siba_get_chiprev(sc->sc_dev) == 1) 1415 tmp = 0x4205017f; 1416 else 1417 tmp = 0x5205017f; 1418 } else { 1419 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID); 1420 tmp = BWN_READ_2(mac, BWN_RFDATALO); 1421 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID); 1422 tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16; 1423 } 1424 phy->rf_rev = (tmp & 0xf0000000) >> 28; 1425 phy->rf_ver = (tmp & 0x0ffff000) >> 12; 1426 phy->rf_manuf = (tmp & 0x00000fff); 1427 1428 /* 1429 * For now, just always do full init (ie, what bwn has traditionally 1430 * done) 1431 */ 1432 phy->phy_do_full_init = 1; 1433 1434 if (phy->rf_manuf != 0x17f) /* 0x17f is broadcom */ 1435 goto unsupradio; 1436 if ((phy->type == BWN_PHYTYPE_A && (phy->rf_ver != 0x2060 || 1437 phy->rf_rev != 1 || phy->rf_manuf != 0x17f)) || 1438 (phy->type == BWN_PHYTYPE_B && (phy->rf_ver & 0xfff0) != 0x2050) || 1439 (phy->type == BWN_PHYTYPE_G && phy->rf_ver != 0x2050) || 1440 (phy->type == BWN_PHYTYPE_N && 1441 phy->rf_ver != 0x2055 && phy->rf_ver != 0x2056) || 1442 (phy->type == BWN_PHYTYPE_LP && 1443 phy->rf_ver != 0x2062 && phy->rf_ver != 0x2063)) 1444 goto unsupradio; 1445 1446 return (0); 1447unsupphy: 1448 device_printf(sc->sc_dev, "unsupported PHY (type %#x, rev %#x, " 1449 "analog %#x)\n", 1450 phy->type, phy->rev, phy->analog); 1451 return (ENXIO); 1452unsupradio: 1453 device_printf(sc->sc_dev, "unsupported radio (manuf %#x, ver %#x, " 1454 "rev %#x)\n", 1455 phy->rf_manuf, phy->rf_ver, phy->rf_rev); 1456 return (ENXIO); 1457} 1458 1459static int 1460bwn_chiptest(struct bwn_mac *mac) 1461{ 1462#define TESTVAL0 0x55aaaa55 1463#define TESTVAL1 0xaa5555aa 1464 struct bwn_softc *sc = mac->mac_sc; 1465 uint32_t v, backup; 1466 1467 BWN_LOCK(sc); 1468 1469 backup = bwn_shm_read_4(mac, BWN_SHARED, 0); 1470 1471 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL0); 1472 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL0) 1473 goto error; 1474 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL1); 1475 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL1) 1476 goto error; 1477 1478 bwn_shm_write_4(mac, BWN_SHARED, 0, backup); 1479 1480 if ((siba_get_revid(sc->sc_dev) >= 3) && 1481 (siba_get_revid(sc->sc_dev) <= 10)) { 1482 BWN_WRITE_2(mac, BWN_TSF_CFP_START, 0xaaaa); 1483 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0xccccbbbb); 1484 if (BWN_READ_2(mac, BWN_TSF_CFP_START_LOW) != 0xbbbb) 1485 goto error; 1486 if (BWN_READ_2(mac, BWN_TSF_CFP_START_HIGH) != 0xcccc) 1487 goto error; 1488 } 1489 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0); 1490 1491 v = BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_GMODE; 1492 if (v != (BWN_MACCTL_GMODE | BWN_MACCTL_IHR_ON)) 1493 goto error; 1494 1495 BWN_UNLOCK(sc); 1496 return (0); 1497error: 1498 BWN_UNLOCK(sc); 1499 device_printf(sc->sc_dev, "failed to validate the chipaccess\n"); 1500 return (ENODEV); 1501} 1502 1503static int 1504bwn_setup_channels(struct bwn_mac *mac, int have_bg, int have_a) 1505{ 1506 struct bwn_softc *sc = mac->mac_sc; 1507 struct ieee80211com *ic = &sc->sc_ic; 1508 uint8_t bands[IEEE80211_MODE_BYTES]; 1509 1510 memset(ic->ic_channels, 0, sizeof(ic->ic_channels)); 1511 ic->ic_nchans = 0; 1512 1513 DPRINTF(sc, BWN_DEBUG_EEPROM, "%s: called; bg=%d, a=%d\n", 1514 __func__, 1515 have_bg, 1516 have_a); 1517 1518 if (have_bg) { 1519 memset(bands, 0, sizeof(bands)); 1520 setbit(bands, IEEE80211_MODE_11B); 1521 setbit(bands, IEEE80211_MODE_11G); 1522 bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX, 1523 &ic->ic_nchans, &bwn_chantable_bg, bands); 1524 } 1525 1526 if (have_a) { 1527 memset(bands, 0, sizeof(bands)); 1528 setbit(bands, IEEE80211_MODE_11A); 1529 bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX, 1530 &ic->ic_nchans, &bwn_chantable_a, bands); 1531 } 1532 1533 mac->mac_phy.supports_2ghz = have_bg; 1534 mac->mac_phy.supports_5ghz = have_a; 1535 1536 return (ic->ic_nchans == 0 ? ENXIO : 0); 1537} 1538 1539uint32_t 1540bwn_shm_read_4(struct bwn_mac *mac, uint16_t way, uint16_t offset) 1541{ 1542 uint32_t ret; 1543 1544 BWN_ASSERT_LOCKED(mac->mac_sc); 1545 1546 if (way == BWN_SHARED) { 1547 KASSERT((offset & 0x0001) == 0, 1548 ("%s:%d warn", __func__, __LINE__)); 1549 if (offset & 0x0003) { 1550 bwn_shm_ctlword(mac, way, offset >> 2); 1551 ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED); 1552 ret <<= 16; 1553 bwn_shm_ctlword(mac, way, (offset >> 2) + 1); 1554 ret |= BWN_READ_2(mac, BWN_SHM_DATA); 1555 goto out; 1556 } 1557 offset >>= 2; 1558 } 1559 bwn_shm_ctlword(mac, way, offset); 1560 ret = BWN_READ_4(mac, BWN_SHM_DATA); 1561out: 1562 return (ret); 1563} 1564 1565uint16_t 1566bwn_shm_read_2(struct bwn_mac *mac, uint16_t way, uint16_t offset) 1567{ 1568 uint16_t ret; 1569 1570 BWN_ASSERT_LOCKED(mac->mac_sc); 1571 1572 if (way == BWN_SHARED) { 1573 KASSERT((offset & 0x0001) == 0, 1574 ("%s:%d warn", __func__, __LINE__)); 1575 if (offset & 0x0003) { 1576 bwn_shm_ctlword(mac, way, offset >> 2); 1577 ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED); 1578 goto out; 1579 } 1580 offset >>= 2; 1581 } 1582 bwn_shm_ctlword(mac, way, offset); 1583 ret = BWN_READ_2(mac, BWN_SHM_DATA); 1584out: 1585 1586 return (ret); 1587} 1588 1589static void 1590bwn_shm_ctlword(struct bwn_mac *mac, uint16_t way, 1591 uint16_t offset) 1592{ 1593 uint32_t control; 1594 1595 control = way; 1596 control <<= 16; 1597 control |= offset; 1598 BWN_WRITE_4(mac, BWN_SHM_CONTROL, control); 1599} 1600 1601void 1602bwn_shm_write_4(struct bwn_mac *mac, uint16_t way, uint16_t offset, 1603 uint32_t value) 1604{ 1605 BWN_ASSERT_LOCKED(mac->mac_sc); 1606 1607 if (way == BWN_SHARED) { 1608 KASSERT((offset & 0x0001) == 0, 1609 ("%s:%d warn", __func__, __LINE__)); 1610 if (offset & 0x0003) { 1611 bwn_shm_ctlword(mac, way, offset >> 2); 1612 BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED, 1613 (value >> 16) & 0xffff); 1614 bwn_shm_ctlword(mac, way, (offset >> 2) + 1); 1615 BWN_WRITE_2(mac, BWN_SHM_DATA, value & 0xffff); 1616 return; 1617 } 1618 offset >>= 2; 1619 } 1620 bwn_shm_ctlword(mac, way, offset); 1621 BWN_WRITE_4(mac, BWN_SHM_DATA, value); 1622} 1623 1624void 1625bwn_shm_write_2(struct bwn_mac *mac, uint16_t way, uint16_t offset, 1626 uint16_t value) 1627{ 1628 BWN_ASSERT_LOCKED(mac->mac_sc); 1629 1630 if (way == BWN_SHARED) { 1631 KASSERT((offset & 0x0001) == 0, 1632 ("%s:%d warn", __func__, __LINE__)); 1633 if (offset & 0x0003) { 1634 bwn_shm_ctlword(mac, way, offset >> 2); 1635 BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED, value); 1636 return; 1637 } 1638 offset >>= 2; 1639 } 1640 bwn_shm_ctlword(mac, way, offset); 1641 BWN_WRITE_2(mac, BWN_SHM_DATA, value); 1642} 1643 1644static void 1645bwn_addchannels(struct ieee80211_channel chans[], int maxchans, int *nchans, 1646 const struct bwn_channelinfo *ci, const uint8_t bands[]) 1647{ 1648 int i, error; 1649 1650 for (i = 0, error = 0; i < ci->nchannels && error == 0; i++) { 1651 const struct bwn_channel *hc = &ci->channels[i]; 1652 1653 error = ieee80211_add_channel(chans, maxchans, nchans, 1654 hc->ieee, hc->freq, hc->maxTxPow, 0, bands); 1655 } 1656} 1657 1658static int 1659bwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1660 const struct ieee80211_bpf_params *params) 1661{ 1662 struct ieee80211com *ic = ni->ni_ic; 1663 struct bwn_softc *sc = ic->ic_softc; 1664 struct bwn_mac *mac = sc->sc_curmac; 1665 int error; 1666 1667 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 || 1668 mac->mac_status < BWN_MAC_STATUS_STARTED) { 1669 m_freem(m); 1670 return (ENETDOWN); 1671 } 1672 1673 BWN_LOCK(sc); 1674 if (bwn_tx_isfull(sc, m)) { 1675 m_freem(m); 1676 BWN_UNLOCK(sc); 1677 return (ENOBUFS); 1678 } 1679 1680 error = bwn_tx_start(sc, ni, m); 1681 if (error == 0) 1682 sc->sc_watchdog_timer = 5; 1683 BWN_UNLOCK(sc); 1684 return (error); 1685} 1686 1687/* 1688 * Callback from the 802.11 layer to update the slot time 1689 * based on the current setting. We use it to notify the 1690 * firmware of ERP changes and the f/w takes care of things 1691 * like slot time and preamble. 1692 */ 1693static void 1694bwn_updateslot(struct ieee80211com *ic) 1695{ 1696 struct bwn_softc *sc = ic->ic_softc; 1697 struct bwn_mac *mac; 1698 1699 BWN_LOCK(sc); 1700 if (sc->sc_flags & BWN_FLAG_RUNNING) { 1701 mac = (struct bwn_mac *)sc->sc_curmac; 1702 bwn_set_slot_time(mac, IEEE80211_GET_SLOTTIME(ic)); 1703 } 1704 BWN_UNLOCK(sc); 1705} 1706 1707/* 1708 * Callback from the 802.11 layer after a promiscuous mode change. 1709 * Note this interface does not check the operating mode as this 1710 * is an internal callback and we are expected to honor the current 1711 * state (e.g. this is used for setting the interface in promiscuous 1712 * mode when operating in hostap mode to do ACS). 1713 */ 1714static void 1715bwn_update_promisc(struct ieee80211com *ic) 1716{ 1717 struct bwn_softc *sc = ic->ic_softc; 1718 struct bwn_mac *mac = sc->sc_curmac; 1719 1720 BWN_LOCK(sc); 1721 mac = sc->sc_curmac; 1722 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1723 if (ic->ic_promisc > 0) 1724 sc->sc_filters |= BWN_MACCTL_PROMISC; 1725 else 1726 sc->sc_filters &= ~BWN_MACCTL_PROMISC; 1727 bwn_set_opmode(mac); 1728 } 1729 BWN_UNLOCK(sc); 1730} 1731 1732/* 1733 * Callback from the 802.11 layer to update WME parameters. 1734 */ 1735static int 1736bwn_wme_update(struct ieee80211com *ic) 1737{ 1738 struct bwn_softc *sc = ic->ic_softc; 1739 struct bwn_mac *mac = sc->sc_curmac; 1740 struct wmeParams *wmep; 1741 int i; 1742 1743 BWN_LOCK(sc); 1744 mac = sc->sc_curmac; 1745 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1746 bwn_mac_suspend(mac); 1747 for (i = 0; i < N(sc->sc_wmeParams); i++) { 1748 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[i]; 1749 bwn_wme_loadparams(mac, wmep, bwn_wme_shm_offsets[i]); 1750 } 1751 bwn_mac_enable(mac); 1752 } 1753 BWN_UNLOCK(sc); 1754 return (0); 1755} 1756 1757static void 1758bwn_scan_start(struct ieee80211com *ic) 1759{ 1760 struct bwn_softc *sc = ic->ic_softc; 1761 struct bwn_mac *mac; 1762 1763 BWN_LOCK(sc); 1764 mac = sc->sc_curmac; 1765 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1766 sc->sc_filters |= BWN_MACCTL_BEACON_PROMISC; 1767 bwn_set_opmode(mac); 1768 /* disable CFP update during scan */ 1769 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_SKIP_CFP_UPDATE); 1770 } 1771 BWN_UNLOCK(sc); 1772} 1773 1774static void 1775bwn_scan_end(struct ieee80211com *ic) 1776{ 1777 struct bwn_softc *sc = ic->ic_softc; 1778 struct bwn_mac *mac; 1779 1780 BWN_LOCK(sc); 1781 mac = sc->sc_curmac; 1782 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1783 sc->sc_filters &= ~BWN_MACCTL_BEACON_PROMISC; 1784 bwn_set_opmode(mac); 1785 bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_SKIP_CFP_UPDATE); 1786 } 1787 BWN_UNLOCK(sc); 1788} 1789 1790static void 1791bwn_set_channel(struct ieee80211com *ic) 1792{ 1793 struct bwn_softc *sc = ic->ic_softc; 1794 struct bwn_mac *mac = sc->sc_curmac; 1795 struct bwn_phy *phy = &mac->mac_phy; 1796 int chan, error; 1797 1798 BWN_LOCK(sc); 1799 1800 error = bwn_switch_band(sc, ic->ic_curchan); 1801 if (error) 1802 goto fail; 1803 bwn_mac_suspend(mac); 1804 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG); 1805 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1806 if (chan != phy->chan) 1807 bwn_switch_channel(mac, chan); 1808 1809 /* TX power level */ 1810 if (ic->ic_curchan->ic_maxpower != 0 && 1811 ic->ic_curchan->ic_maxpower != phy->txpower) { 1812 phy->txpower = ic->ic_curchan->ic_maxpower / 2; 1813 bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME | 1814 BWN_TXPWR_IGNORE_TSSI); 1815 } 1816 1817 bwn_set_txantenna(mac, BWN_ANT_DEFAULT); 1818 if (phy->set_antenna) 1819 phy->set_antenna(mac, BWN_ANT_DEFAULT); 1820 1821 if (sc->sc_rf_enabled != phy->rf_on) { 1822 if (sc->sc_rf_enabled) { 1823 bwn_rf_turnon(mac); 1824 if (!(mac->mac_flags & BWN_MAC_FLAG_RADIO_ON)) 1825 device_printf(sc->sc_dev, 1826 "please turn on the RF switch\n"); 1827 } else 1828 bwn_rf_turnoff(mac); 1829 } 1830 1831 bwn_mac_enable(mac); 1832 1833fail: 1834 BWN_UNLOCK(sc); 1835} 1836 1837static struct ieee80211vap * 1838bwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1839 enum ieee80211_opmode opmode, int flags, 1840 const uint8_t bssid[IEEE80211_ADDR_LEN], 1841 const uint8_t mac[IEEE80211_ADDR_LEN]) 1842{ 1843 struct ieee80211vap *vap; 1844 struct bwn_vap *bvp; 1845 1846 switch (opmode) { 1847 case IEEE80211_M_HOSTAP: 1848 case IEEE80211_M_MBSS: 1849 case IEEE80211_M_STA: 1850 case IEEE80211_M_WDS: 1851 case IEEE80211_M_MONITOR: 1852 case IEEE80211_M_IBSS: 1853 case IEEE80211_M_AHDEMO: 1854 break; 1855 default: 1856 return (NULL); 1857 } 1858 1859 bvp = malloc(sizeof(struct bwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1860 vap = &bvp->bv_vap; 1861 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 1862 /* override with driver methods */ 1863 bvp->bv_newstate = vap->iv_newstate; 1864 vap->iv_newstate = bwn_newstate; 1865 1866 /* override max aid so sta's cannot assoc when we're out of sta id's */ 1867 vap->iv_max_aid = BWN_STAID_MAX; 1868 1869 ieee80211_ratectl_init(vap); 1870 1871 /* complete setup */ 1872 ieee80211_vap_attach(vap, ieee80211_media_change, 1873 ieee80211_media_status, mac); 1874 return (vap); 1875} 1876 1877static void 1878bwn_vap_delete(struct ieee80211vap *vap) 1879{ 1880 struct bwn_vap *bvp = BWN_VAP(vap); 1881 1882 ieee80211_ratectl_deinit(vap); 1883 ieee80211_vap_detach(vap); 1884 free(bvp, M_80211_VAP); 1885} 1886 1887static int 1888bwn_init(struct bwn_softc *sc) 1889{ 1890 struct bwn_mac *mac; 1891 int error; 1892 1893 BWN_ASSERT_LOCKED(sc); 1894 1895 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__); 1896 1897 bzero(sc->sc_bssid, IEEE80211_ADDR_LEN); 1898 sc->sc_flags |= BWN_FLAG_NEED_BEACON_TP; 1899 sc->sc_filters = 0; 1900 bwn_wme_clear(sc); 1901 sc->sc_beacons[0] = sc->sc_beacons[1] = 0; 1902 sc->sc_rf_enabled = 1; 1903 1904 mac = sc->sc_curmac; 1905 if (mac->mac_status == BWN_MAC_STATUS_UNINIT) { 1906 error = bwn_core_init(mac); 1907 if (error != 0) 1908 return (error); 1909 } 1910 if (mac->mac_status == BWN_MAC_STATUS_INITED) 1911 bwn_core_start(mac); 1912 1913 bwn_set_opmode(mac); 1914 bwn_set_pretbtt(mac); 1915 bwn_spu_setdelay(mac, 0); 1916 bwn_set_macaddr(mac); 1917 1918 sc->sc_flags |= BWN_FLAG_RUNNING; 1919 callout_reset(&sc->sc_rfswitch_ch, hz, bwn_rfswitch, sc); 1920 callout_reset(&sc->sc_watchdog_ch, hz, bwn_watchdog, sc); 1921 1922 return (0); 1923} 1924 1925static void 1926bwn_stop(struct bwn_softc *sc) 1927{ 1928 struct bwn_mac *mac = sc->sc_curmac; 1929 1930 BWN_ASSERT_LOCKED(sc); 1931 1932 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__); 1933 1934 if (mac->mac_status >= BWN_MAC_STATUS_INITED) { 1935 /* XXX FIXME opmode not based on VAP */ 1936 bwn_set_opmode(mac); 1937 bwn_set_macaddr(mac); 1938 } 1939 1940 if (mac->mac_status >= BWN_MAC_STATUS_STARTED) 1941 bwn_core_stop(mac); 1942 1943 callout_stop(&sc->sc_led_blink_ch); 1944 sc->sc_led_blinking = 0; 1945 1946 bwn_core_exit(mac); 1947 sc->sc_rf_enabled = 0; 1948 1949 sc->sc_flags &= ~BWN_FLAG_RUNNING; 1950} 1951 1952static void 1953bwn_wme_clear(struct bwn_softc *sc) 1954{ 1955#define MS(_v, _f) (((_v) & _f) >> _f##_S) 1956 struct wmeParams *p; 1957 unsigned int i; 1958 1959 KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams), 1960 ("%s:%d: fail", __func__, __LINE__)); 1961 1962 for (i = 0; i < N(sc->sc_wmeParams); i++) { 1963 p = &(sc->sc_wmeParams[i]); 1964 1965 switch (bwn_wme_shm_offsets[i]) { 1966 case BWN_WME_VOICE: 1967 p->wmep_txopLimit = 0; 1968 p->wmep_aifsn = 2; 1969 /* XXX FIXME: log2(cwmin) */ 1970 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 1971 p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX); 1972 break; 1973 case BWN_WME_VIDEO: 1974 p->wmep_txopLimit = 0; 1975 p->wmep_aifsn = 2; 1976 /* XXX FIXME: log2(cwmin) */ 1977 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 1978 p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX); 1979 break; 1980 case BWN_WME_BESTEFFORT: 1981 p->wmep_txopLimit = 0; 1982 p->wmep_aifsn = 3; 1983 /* XXX FIXME: log2(cwmin) */ 1984 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 1985 p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX); 1986 break; 1987 case BWN_WME_BACKGROUND: 1988 p->wmep_txopLimit = 0; 1989 p->wmep_aifsn = 7; 1990 /* XXX FIXME: log2(cwmin) */ 1991 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 1992 p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX); 1993 break; 1994 default: 1995 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 1996 } 1997 } 1998} 1999 2000static int 2001bwn_core_init(struct bwn_mac *mac) 2002{ 2003 struct bwn_softc *sc = mac->mac_sc; 2004 uint64_t hf; 2005 int error; 2006 2007 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT, 2008 ("%s:%d: fail", __func__, __LINE__)); 2009 2010 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__); 2011 2012 siba_powerup(sc->sc_dev, 0); 2013 if (!siba_dev_isup(sc->sc_dev)) 2014 bwn_reset_core(mac, mac->mac_phy.gmode); 2015 2016 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID; 2017 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON; 2018 mac->mac_phy.hwpctl = (bwn_hwpctl) ? 1 : 0; 2019 BWN_GETTIME(mac->mac_phy.nexttime); 2020 mac->mac_phy.txerrors = BWN_TXERROR_MAX; 2021 bzero(&mac->mac_stats, sizeof(mac->mac_stats)); 2022 mac->mac_stats.link_noise = -95; 2023 mac->mac_reason_intr = 0; 2024 bzero(mac->mac_reason, sizeof(mac->mac_reason)); 2025 mac->mac_intr_mask = BWN_INTR_MASKTEMPLATE; 2026#ifdef BWN_DEBUG 2027 if (sc->sc_debug & BWN_DEBUG_XMIT) 2028 mac->mac_intr_mask &= ~BWN_INTR_PHY_TXERR; 2029#endif 2030 mac->mac_suspended = 1; 2031 mac->mac_task_state = 0; 2032 memset(&mac->mac_noise, 0, sizeof(mac->mac_noise)); 2033 2034 mac->mac_phy.init_pre(mac); 2035 2036 siba_pcicore_intr(sc->sc_dev); 2037 2038 siba_fix_imcfglobug(sc->sc_dev); 2039 bwn_bt_disable(mac); 2040 if (mac->mac_phy.prepare_hw) { 2041 error = mac->mac_phy.prepare_hw(mac); 2042 if (error) 2043 goto fail0; 2044 } 2045 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: chip_init\n", __func__); 2046 error = bwn_chip_init(mac); 2047 if (error) 2048 goto fail0; 2049 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_COREREV, 2050 siba_get_revid(sc->sc_dev)); 2051 hf = bwn_hf_read(mac); 2052 if (mac->mac_phy.type == BWN_PHYTYPE_G) { 2053 hf |= BWN_HF_GPHY_SYM_WORKAROUND; 2054 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL) 2055 hf |= BWN_HF_PAGAINBOOST_OFDM_ON; 2056 if (mac->mac_phy.rev == 1) 2057 hf |= BWN_HF_GPHY_DC_CANCELFILTER; 2058 } 2059 if (mac->mac_phy.rf_ver == 0x2050) { 2060 if (mac->mac_phy.rf_rev < 6) 2061 hf |= BWN_HF_FORCE_VCO_RECALC; 2062 if (mac->mac_phy.rf_rev == 6) 2063 hf |= BWN_HF_4318_TSSI; 2064 } 2065 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW) 2066 hf |= BWN_HF_SLOWCLOCK_REQ_OFF; 2067 if ((siba_get_type(sc->sc_dev) == SIBA_TYPE_PCI) && 2068 (siba_get_pcicore_revid(sc->sc_dev) <= 10)) 2069 hf |= BWN_HF_PCI_SLOWCLOCK_WORKAROUND; 2070 hf &= ~BWN_HF_SKIP_CFP_UPDATE; 2071 bwn_hf_write(mac, hf); 2072 2073 /* Tell the firmware about the MAC capabilities */ 2074 if (siba_get_revid(sc->sc_dev) >= 13) { 2075 uint32_t cap; 2076 cap = BWN_READ_4(mac, BWN_MAC_HW_CAP); 2077 DPRINTF(sc, BWN_DEBUG_RESET, 2078 "%s: hw capabilities: 0x%08x\n", 2079 __func__, cap); 2080 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_L, 2081 cap & 0xffff); 2082 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_H, 2083 (cap >> 16) & 0xffff); 2084 } 2085 2086 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG); 2087 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SHORT_RETRY_FALLBACK, 3); 2088 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_LONG_RETRY_FALLBACK, 2); 2089 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_MAXTIME, 1); 2090 2091 bwn_rate_init(mac); 2092 bwn_set_phytxctl(mac); 2093 2094 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MIN, 2095 (mac->mac_phy.type == BWN_PHYTYPE_B) ? 0x1f : 0xf); 2096 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MAX, 0x3ff); 2097 2098 if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0) 2099 bwn_pio_init(mac); 2100 else 2101 bwn_dma_init(mac); 2102 bwn_wme_init(mac); 2103 bwn_spu_setdelay(mac, 1); 2104 bwn_bt_enable(mac); 2105 2106 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: powerup\n", __func__); 2107 siba_powerup(sc->sc_dev, 2108 !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW)); 2109 bwn_set_macaddr(mac); 2110 bwn_crypt_init(mac); 2111 2112 /* XXX LED initializatin */ 2113 2114 mac->mac_status = BWN_MAC_STATUS_INITED; 2115 2116 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: done\n", __func__); 2117 return (error); 2118 2119fail0: 2120 siba_powerdown(sc->sc_dev); 2121 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT, 2122 ("%s:%d: fail", __func__, __LINE__)); 2123 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: fail\n", __func__); 2124 return (error); 2125} 2126 2127static void 2128bwn_core_start(struct bwn_mac *mac) 2129{ 2130 struct bwn_softc *sc = mac->mac_sc; 2131 uint32_t tmp; 2132 2133 KASSERT(mac->mac_status == BWN_MAC_STATUS_INITED, 2134 ("%s:%d: fail", __func__, __LINE__)); 2135 2136 if (siba_get_revid(sc->sc_dev) < 5) 2137 return; 2138 2139 while (1) { 2140 tmp = BWN_READ_4(mac, BWN_XMITSTAT_0); 2141 if (!(tmp & 0x00000001)) 2142 break; 2143 tmp = BWN_READ_4(mac, BWN_XMITSTAT_1); 2144 } 2145 2146 bwn_mac_enable(mac); 2147 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask); 2148 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac); 2149 2150 mac->mac_status = BWN_MAC_STATUS_STARTED; 2151} 2152 2153static void 2154bwn_core_exit(struct bwn_mac *mac) 2155{ 2156 struct bwn_softc *sc = mac->mac_sc; 2157 uint32_t macctl; 2158 2159 BWN_ASSERT_LOCKED(mac->mac_sc); 2160 2161 KASSERT(mac->mac_status <= BWN_MAC_STATUS_INITED, 2162 ("%s:%d: fail", __func__, __LINE__)); 2163 2164 if (mac->mac_status != BWN_MAC_STATUS_INITED) 2165 return; 2166 mac->mac_status = BWN_MAC_STATUS_UNINIT; 2167 2168 macctl = BWN_READ_4(mac, BWN_MACCTL); 2169 macctl &= ~BWN_MACCTL_MCODE_RUN; 2170 macctl |= BWN_MACCTL_MCODE_JMP0; 2171 BWN_WRITE_4(mac, BWN_MACCTL, macctl); 2172 2173 bwn_dma_stop(mac); 2174 bwn_pio_stop(mac); 2175 bwn_chip_exit(mac); 2176 mac->mac_phy.switch_analog(mac, 0); 2177 siba_dev_down(sc->sc_dev, 0); 2178 siba_powerdown(sc->sc_dev); 2179} 2180 2181static void 2182bwn_bt_disable(struct bwn_mac *mac) 2183{ 2184 struct bwn_softc *sc = mac->mac_sc; 2185 2186 (void)sc; 2187 /* XXX do nothing yet */ 2188} 2189 2190static int 2191bwn_chip_init(struct bwn_mac *mac) 2192{ 2193 struct bwn_softc *sc = mac->mac_sc; 2194 struct bwn_phy *phy = &mac->mac_phy; 2195 uint32_t macctl; 2196 int error; 2197 2198 macctl = BWN_MACCTL_IHR_ON | BWN_MACCTL_SHM_ON | BWN_MACCTL_STA; 2199 if (phy->gmode) 2200 macctl |= BWN_MACCTL_GMODE; 2201 BWN_WRITE_4(mac, BWN_MACCTL, macctl); 2202 2203 error = bwn_fw_fillinfo(mac); 2204 if (error) 2205 return (error); 2206 error = bwn_fw_loaducode(mac); 2207 if (error) 2208 return (error); 2209 2210 error = bwn_gpio_init(mac); 2211 if (error) 2212 return (error); 2213 2214 error = bwn_fw_loadinitvals(mac); 2215 if (error) { 2216 siba_gpio_set(sc->sc_dev, 0); 2217 return (error); 2218 } 2219 phy->switch_analog(mac, 1); 2220 error = bwn_phy_init(mac); 2221 if (error) { 2222 siba_gpio_set(sc->sc_dev, 0); 2223 return (error); 2224 } 2225 if (phy->set_im) 2226 phy->set_im(mac, BWN_IMMODE_NONE); 2227 if (phy->set_antenna) 2228 phy->set_antenna(mac, BWN_ANT_DEFAULT); 2229 bwn_set_txantenna(mac, BWN_ANT_DEFAULT); 2230 2231 if (phy->type == BWN_PHYTYPE_B) 2232 BWN_WRITE_2(mac, 0x005e, BWN_READ_2(mac, 0x005e) | 0x0004); 2233 BWN_WRITE_4(mac, 0x0100, 0x01000000); 2234 if (siba_get_revid(sc->sc_dev) < 5) 2235 BWN_WRITE_4(mac, 0x010c, 0x01000000); 2236 2237 BWN_WRITE_4(mac, BWN_MACCTL, 2238 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_STA); 2239 BWN_WRITE_4(mac, BWN_MACCTL, 2240 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_STA); 2241 bwn_shm_write_2(mac, BWN_SHARED, 0x0074, 0x0000); 2242 2243 bwn_set_opmode(mac); 2244 if (siba_get_revid(sc->sc_dev) < 3) { 2245 BWN_WRITE_2(mac, 0x060e, 0x0000); 2246 BWN_WRITE_2(mac, 0x0610, 0x8000); 2247 BWN_WRITE_2(mac, 0x0604, 0x0000); 2248 BWN_WRITE_2(mac, 0x0606, 0x0200); 2249 } else { 2250 BWN_WRITE_4(mac, 0x0188, 0x80000000); 2251 BWN_WRITE_4(mac, 0x018c, 0x02000000); 2252 } 2253 BWN_WRITE_4(mac, BWN_INTR_REASON, 0x00004000); 2254 BWN_WRITE_4(mac, BWN_DMA0_INTR_MASK, 0x0001dc00); 2255 BWN_WRITE_4(mac, BWN_DMA1_INTR_MASK, 0x0000dc00); 2256 BWN_WRITE_4(mac, BWN_DMA2_INTR_MASK, 0x0000dc00); 2257 BWN_WRITE_4(mac, BWN_DMA3_INTR_MASK, 0x0001dc00); 2258 BWN_WRITE_4(mac, BWN_DMA4_INTR_MASK, 0x0000dc00); 2259 BWN_WRITE_4(mac, BWN_DMA5_INTR_MASK, 0x0000dc00); 2260 2261 bwn_mac_phy_clock_set(mac, true); 2262 2263 /* SIBA powerup */ 2264 /* XXX TODO: BCMA powerup */ 2265 BWN_WRITE_2(mac, BWN_POWERUP_DELAY, siba_get_cc_powerdelay(sc->sc_dev)); 2266 return (error); 2267} 2268 2269/* read hostflags */ 2270uint64_t 2271bwn_hf_read(struct bwn_mac *mac) 2272{ 2273 uint64_t ret; 2274 2275 ret = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFHI); 2276 ret <<= 16; 2277 ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFMI); 2278 ret <<= 16; 2279 ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFLO); 2280 return (ret); 2281} 2282 2283void 2284bwn_hf_write(struct bwn_mac *mac, uint64_t value) 2285{ 2286 2287 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFLO, 2288 (value & 0x00000000ffffull)); 2289 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFMI, 2290 (value & 0x0000ffff0000ull) >> 16); 2291 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFHI, 2292 (value & 0xffff00000000ULL) >> 32); 2293} 2294 2295static void 2296bwn_set_txretry(struct bwn_mac *mac, int s, int l) 2297{ 2298 2299 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_SHORT_RETRY, MIN(s, 0xf)); 2300 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_LONG_RETRY, MIN(l, 0xf)); 2301} 2302 2303static void 2304bwn_rate_init(struct bwn_mac *mac) 2305{ 2306 2307 switch (mac->mac_phy.type) { 2308 case BWN_PHYTYPE_A: 2309 case BWN_PHYTYPE_G: 2310 case BWN_PHYTYPE_LP: 2311 case BWN_PHYTYPE_N: 2312 bwn_rate_write(mac, BWN_OFDM_RATE_6MB, 1); 2313 bwn_rate_write(mac, BWN_OFDM_RATE_12MB, 1); 2314 bwn_rate_write(mac, BWN_OFDM_RATE_18MB, 1); 2315 bwn_rate_write(mac, BWN_OFDM_RATE_24MB, 1); 2316 bwn_rate_write(mac, BWN_OFDM_RATE_36MB, 1); 2317 bwn_rate_write(mac, BWN_OFDM_RATE_48MB, 1); 2318 bwn_rate_write(mac, BWN_OFDM_RATE_54MB, 1); 2319 if (mac->mac_phy.type == BWN_PHYTYPE_A) 2320 break; 2321 /* FALLTHROUGH */ 2322 case BWN_PHYTYPE_B: 2323 bwn_rate_write(mac, BWN_CCK_RATE_1MB, 0); 2324 bwn_rate_write(mac, BWN_CCK_RATE_2MB, 0); 2325 bwn_rate_write(mac, BWN_CCK_RATE_5MB, 0); 2326 bwn_rate_write(mac, BWN_CCK_RATE_11MB, 0); 2327 break; 2328 default: 2329 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2330 } 2331} 2332 2333static void 2334bwn_rate_write(struct bwn_mac *mac, uint16_t rate, int ofdm) 2335{ 2336 uint16_t offset; 2337 2338 if (ofdm) { 2339 offset = 0x480; 2340 offset += (bwn_plcp_getofdm(rate) & 0x000f) * 2; 2341 } else { 2342 offset = 0x4c0; 2343 offset += (bwn_plcp_getcck(rate) & 0x000f) * 2; 2344 } 2345 bwn_shm_write_2(mac, BWN_SHARED, offset + 0x20, 2346 bwn_shm_read_2(mac, BWN_SHARED, offset)); 2347} 2348 2349static uint8_t 2350bwn_plcp_getcck(const uint8_t bitrate) 2351{ 2352 2353 switch (bitrate) { 2354 case BWN_CCK_RATE_1MB: 2355 return (0x0a); 2356 case BWN_CCK_RATE_2MB: 2357 return (0x14); 2358 case BWN_CCK_RATE_5MB: 2359 return (0x37); 2360 case BWN_CCK_RATE_11MB: 2361 return (0x6e); 2362 } 2363 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2364 return (0); 2365} 2366 2367static uint8_t 2368bwn_plcp_getofdm(const uint8_t bitrate) 2369{ 2370 2371 switch (bitrate) { 2372 case BWN_OFDM_RATE_6MB: 2373 return (0xb); 2374 case BWN_OFDM_RATE_9MB: 2375 return (0xf); 2376 case BWN_OFDM_RATE_12MB: 2377 return (0xa); 2378 case BWN_OFDM_RATE_18MB: 2379 return (0xe); 2380 case BWN_OFDM_RATE_24MB: 2381 return (0x9); 2382 case BWN_OFDM_RATE_36MB: 2383 return (0xd); 2384 case BWN_OFDM_RATE_48MB: 2385 return (0x8); 2386 case BWN_OFDM_RATE_54MB: 2387 return (0xc); 2388 } 2389 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2390 return (0); 2391} 2392 2393static void 2394bwn_set_phytxctl(struct bwn_mac *mac) 2395{ 2396 uint16_t ctl; 2397 2398 ctl = (BWN_TX_PHY_ENC_CCK | BWN_TX_PHY_ANT01AUTO | 2399 BWN_TX_PHY_TXPWR); 2400 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_BEACON_PHYCTL, ctl); 2401 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, ctl); 2402 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, ctl); 2403} 2404 2405static void 2406bwn_pio_init(struct bwn_mac *mac) 2407{ 2408 struct bwn_pio *pio = &mac->mac_method.pio; 2409 2410 BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL) 2411 & ~BWN_MACCTL_BIGENDIAN); 2412 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_RX_PADOFFSET, 0); 2413 2414 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BK], 0); 2415 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BE], 1); 2416 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VI], 2); 2417 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VO], 3); 2418 bwn_pio_set_txqueue(mac, &pio->mcast, 4); 2419 bwn_pio_setupqueue_rx(mac, &pio->rx, 0); 2420} 2421 2422static void 2423bwn_pio_set_txqueue(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 2424 int index) 2425{ 2426 struct bwn_pio_txpkt *tp; 2427 struct bwn_softc *sc = mac->mac_sc; 2428 unsigned int i; 2429 2430 tq->tq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_TXQOFFSET(mac); 2431 tq->tq_index = index; 2432 2433 tq->tq_free = BWN_PIO_MAX_TXPACKETS; 2434 if (siba_get_revid(sc->sc_dev) >= 8) 2435 tq->tq_size = 1920; 2436 else { 2437 tq->tq_size = bwn_pio_read_2(mac, tq, BWN_PIO_TXQBUFSIZE); 2438 tq->tq_size -= 80; 2439 } 2440 2441 TAILQ_INIT(&tq->tq_pktlist); 2442 for (i = 0; i < N(tq->tq_pkts); i++) { 2443 tp = &(tq->tq_pkts[i]); 2444 tp->tp_index = i; 2445 tp->tp_queue = tq; 2446 TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list); 2447 } 2448} 2449 2450static uint16_t 2451bwn_pio_idx2base(struct bwn_mac *mac, int index) 2452{ 2453 struct bwn_softc *sc = mac->mac_sc; 2454 static const uint16_t bases[] = { 2455 BWN_PIO_BASE0, 2456 BWN_PIO_BASE1, 2457 BWN_PIO_BASE2, 2458 BWN_PIO_BASE3, 2459 BWN_PIO_BASE4, 2460 BWN_PIO_BASE5, 2461 BWN_PIO_BASE6, 2462 BWN_PIO_BASE7, 2463 }; 2464 static const uint16_t bases_rev11[] = { 2465 BWN_PIO11_BASE0, 2466 BWN_PIO11_BASE1, 2467 BWN_PIO11_BASE2, 2468 BWN_PIO11_BASE3, 2469 BWN_PIO11_BASE4, 2470 BWN_PIO11_BASE5, 2471 }; 2472 2473 if (siba_get_revid(sc->sc_dev) >= 11) { 2474 if (index >= N(bases_rev11)) 2475 device_printf(sc->sc_dev, "%s: warning\n", __func__); 2476 return (bases_rev11[index]); 2477 } 2478 if (index >= N(bases)) 2479 device_printf(sc->sc_dev, "%s: warning\n", __func__); 2480 return (bases[index]); 2481} 2482 2483static void 2484bwn_pio_setupqueue_rx(struct bwn_mac *mac, struct bwn_pio_rxqueue *prq, 2485 int index) 2486{ 2487 struct bwn_softc *sc = mac->mac_sc; 2488 2489 prq->prq_mac = mac; 2490 prq->prq_rev = siba_get_revid(sc->sc_dev); 2491 prq->prq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_RXQOFFSET(mac); 2492 bwn_dma_rxdirectfifo(mac, index, 1); 2493} 2494 2495static void 2496bwn_destroy_pioqueue_tx(struct bwn_pio_txqueue *tq) 2497{ 2498 if (tq == NULL) 2499 return; 2500 bwn_pio_cancel_tx_packets(tq); 2501} 2502 2503static void 2504bwn_destroy_queue_tx(struct bwn_pio_txqueue *pio) 2505{ 2506 2507 bwn_destroy_pioqueue_tx(pio); 2508} 2509 2510static uint16_t 2511bwn_pio_read_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 2512 uint16_t offset) 2513{ 2514 2515 return (BWN_READ_2(mac, tq->tq_base + offset)); 2516} 2517 2518static void 2519bwn_dma_rxdirectfifo(struct bwn_mac *mac, int idx, uint8_t enable) 2520{ 2521 uint32_t ctl; 2522 int type; 2523 uint16_t base; 2524 2525 type = bwn_dma_mask2type(bwn_dma_mask(mac)); 2526 base = bwn_dma_base(type, idx); 2527 if (type == BWN_DMA_64BIT) { 2528 ctl = BWN_READ_4(mac, base + BWN_DMA64_RXCTL); 2529 ctl &= ~BWN_DMA64_RXDIRECTFIFO; 2530 if (enable) 2531 ctl |= BWN_DMA64_RXDIRECTFIFO; 2532 BWN_WRITE_4(mac, base + BWN_DMA64_RXCTL, ctl); 2533 } else { 2534 ctl = BWN_READ_4(mac, base + BWN_DMA32_RXCTL); 2535 ctl &= ~BWN_DMA32_RXDIRECTFIFO; 2536 if (enable) 2537 ctl |= BWN_DMA32_RXDIRECTFIFO; 2538 BWN_WRITE_4(mac, base + BWN_DMA32_RXCTL, ctl); 2539 } 2540} 2541 2542static uint64_t 2543bwn_dma_mask(struct bwn_mac *mac) 2544{ 2545 uint32_t tmp; 2546 uint16_t base; 2547 2548 tmp = BWN_READ_4(mac, SIBA_TGSHIGH); 2549 if (tmp & SIBA_TGSHIGH_DMA64) 2550 return (BWN_DMA_BIT_MASK(64)); 2551 base = bwn_dma_base(0, 0); 2552 BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK); 2553 tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL); 2554 if (tmp & BWN_DMA32_TXADDREXT_MASK) 2555 return (BWN_DMA_BIT_MASK(32)); 2556 2557 return (BWN_DMA_BIT_MASK(30)); 2558} 2559 2560static int 2561bwn_dma_mask2type(uint64_t dmamask) 2562{ 2563 2564 if (dmamask == BWN_DMA_BIT_MASK(30)) 2565 return (BWN_DMA_30BIT); 2566 if (dmamask == BWN_DMA_BIT_MASK(32)) 2567 return (BWN_DMA_32BIT); 2568 if (dmamask == BWN_DMA_BIT_MASK(64)) 2569 return (BWN_DMA_64BIT); 2570 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2571 return (BWN_DMA_30BIT); 2572} 2573 2574static void 2575bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *tq) 2576{ 2577 struct bwn_pio_txpkt *tp; 2578 unsigned int i; 2579 2580 for (i = 0; i < N(tq->tq_pkts); i++) { 2581 tp = &(tq->tq_pkts[i]); 2582 if (tp->tp_m) { 2583 m_freem(tp->tp_m); 2584 tp->tp_m = NULL; 2585 } 2586 } 2587} 2588 2589static uint16_t 2590bwn_dma_base(int type, int controller_idx) 2591{ 2592 static const uint16_t map64[] = { 2593 BWN_DMA64_BASE0, 2594 BWN_DMA64_BASE1, 2595 BWN_DMA64_BASE2, 2596 BWN_DMA64_BASE3, 2597 BWN_DMA64_BASE4, 2598 BWN_DMA64_BASE5, 2599 }; 2600 static const uint16_t map32[] = { 2601 BWN_DMA32_BASE0, 2602 BWN_DMA32_BASE1, 2603 BWN_DMA32_BASE2, 2604 BWN_DMA32_BASE3, 2605 BWN_DMA32_BASE4, 2606 BWN_DMA32_BASE5, 2607 }; 2608 2609 if (type == BWN_DMA_64BIT) { 2610 KASSERT(controller_idx >= 0 && controller_idx < N(map64), 2611 ("%s:%d: fail", __func__, __LINE__)); 2612 return (map64[controller_idx]); 2613 } 2614 KASSERT(controller_idx >= 0 && controller_idx < N(map32), 2615 ("%s:%d: fail", __func__, __LINE__)); 2616 return (map32[controller_idx]); 2617} 2618 2619static void 2620bwn_dma_init(struct bwn_mac *mac) 2621{ 2622 struct bwn_dma *dma = &mac->mac_method.dma; 2623 2624 /* setup TX DMA channels. */ 2625 bwn_dma_setup(dma->wme[WME_AC_BK]); 2626 bwn_dma_setup(dma->wme[WME_AC_BE]); 2627 bwn_dma_setup(dma->wme[WME_AC_VI]); 2628 bwn_dma_setup(dma->wme[WME_AC_VO]); 2629 bwn_dma_setup(dma->mcast); 2630 /* setup RX DMA channel. */ 2631 bwn_dma_setup(dma->rx); 2632} 2633 2634static struct bwn_dma_ring * 2635bwn_dma_ringsetup(struct bwn_mac *mac, int controller_index, 2636 int for_tx, int type) 2637{ 2638 struct bwn_dma *dma = &mac->mac_method.dma; 2639 struct bwn_dma_ring *dr; 2640 struct bwn_dmadesc_generic *desc; 2641 struct bwn_dmadesc_meta *mt; 2642 struct bwn_softc *sc = mac->mac_sc; 2643 int error, i; 2644 2645 dr = malloc(sizeof(*dr), M_DEVBUF, M_NOWAIT | M_ZERO); 2646 if (dr == NULL) 2647 goto out; 2648 dr->dr_numslots = BWN_RXRING_SLOTS; 2649 if (for_tx) 2650 dr->dr_numslots = BWN_TXRING_SLOTS; 2651 2652 dr->dr_meta = malloc(dr->dr_numslots * sizeof(struct bwn_dmadesc_meta), 2653 M_DEVBUF, M_NOWAIT | M_ZERO); 2654 if (dr->dr_meta == NULL) 2655 goto fail0; 2656 2657 dr->dr_type = type; 2658 dr->dr_mac = mac; 2659 dr->dr_base = bwn_dma_base(type, controller_index); 2660 dr->dr_index = controller_index; 2661 if (type == BWN_DMA_64BIT) { 2662 dr->getdesc = bwn_dma_64_getdesc; 2663 dr->setdesc = bwn_dma_64_setdesc; 2664 dr->start_transfer = bwn_dma_64_start_transfer; 2665 dr->suspend = bwn_dma_64_suspend; 2666 dr->resume = bwn_dma_64_resume; 2667 dr->get_curslot = bwn_dma_64_get_curslot; 2668 dr->set_curslot = bwn_dma_64_set_curslot; 2669 } else { 2670 dr->getdesc = bwn_dma_32_getdesc; 2671 dr->setdesc = bwn_dma_32_setdesc; 2672 dr->start_transfer = bwn_dma_32_start_transfer; 2673 dr->suspend = bwn_dma_32_suspend; 2674 dr->resume = bwn_dma_32_resume; 2675 dr->get_curslot = bwn_dma_32_get_curslot; 2676 dr->set_curslot = bwn_dma_32_set_curslot; 2677 } 2678 if (for_tx) { 2679 dr->dr_tx = 1; 2680 dr->dr_curslot = -1; 2681 } else { 2682 if (dr->dr_index == 0) { 2683 switch (mac->mac_fw.fw_hdr_format) { 2684 case BWN_FW_HDR_351: 2685 case BWN_FW_HDR_410: 2686 dr->dr_rx_bufsize = 2687 BWN_DMA0_RX_BUFFERSIZE_FW351; 2688 dr->dr_frameoffset = 2689 BWN_DMA0_RX_FRAMEOFFSET_FW351; 2690 break; 2691 case BWN_FW_HDR_598: 2692 dr->dr_rx_bufsize = 2693 BWN_DMA0_RX_BUFFERSIZE_FW598; 2694 dr->dr_frameoffset = 2695 BWN_DMA0_RX_FRAMEOFFSET_FW598; 2696 break; 2697 } 2698 } else 2699 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2700 } 2701 2702 error = bwn_dma_allocringmemory(dr); 2703 if (error) 2704 goto fail2; 2705 2706 if (for_tx) { 2707 /* 2708 * Assumption: BWN_TXRING_SLOTS can be divided by 2709 * BWN_TX_SLOTS_PER_FRAME 2710 */ 2711 KASSERT(BWN_TXRING_SLOTS % BWN_TX_SLOTS_PER_FRAME == 0, 2712 ("%s:%d: fail", __func__, __LINE__)); 2713 2714 dr->dr_txhdr_cache = contigmalloc( 2715 (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * 2716 BWN_MAXTXHDRSIZE, M_DEVBUF, M_ZERO, 2717 0, BUS_SPACE_MAXADDR, 8, 0); 2718 if (dr->dr_txhdr_cache == NULL) { 2719 device_printf(sc->sc_dev, 2720 "can't allocate TX header DMA memory\n"); 2721 goto fail1; 2722 } 2723 2724 /* 2725 * Create TX ring DMA stuffs 2726 */ 2727 error = bus_dma_tag_create(dma->parent_dtag, 2728 BWN_ALIGN, 0, 2729 BUS_SPACE_MAXADDR, 2730 BUS_SPACE_MAXADDR, 2731 NULL, NULL, 2732 BWN_HDRSIZE(mac), 2733 1, 2734 BUS_SPACE_MAXSIZE_32BIT, 2735 0, 2736 NULL, NULL, 2737 &dr->dr_txring_dtag); 2738 if (error) { 2739 device_printf(sc->sc_dev, 2740 "can't create TX ring DMA tag: TODO frees\n"); 2741 goto fail2; 2742 } 2743 2744 for (i = 0; i < dr->dr_numslots; i += 2) { 2745 dr->getdesc(dr, i, &desc, &mt); 2746 2747 mt->mt_txtype = BWN_DMADESC_METATYPE_HEADER; 2748 mt->mt_m = NULL; 2749 mt->mt_ni = NULL; 2750 mt->mt_islast = 0; 2751 error = bus_dmamap_create(dr->dr_txring_dtag, 0, 2752 &mt->mt_dmap); 2753 if (error) { 2754 device_printf(sc->sc_dev, 2755 "can't create RX buf DMA map\n"); 2756 goto fail2; 2757 } 2758 2759 dr->getdesc(dr, i + 1, &desc, &mt); 2760 2761 mt->mt_txtype = BWN_DMADESC_METATYPE_BODY; 2762 mt->mt_m = NULL; 2763 mt->mt_ni = NULL; 2764 mt->mt_islast = 1; 2765 error = bus_dmamap_create(dma->txbuf_dtag, 0, 2766 &mt->mt_dmap); 2767 if (error) { 2768 device_printf(sc->sc_dev, 2769 "can't create RX buf DMA map\n"); 2770 goto fail2; 2771 } 2772 } 2773 } else { 2774 error = bus_dmamap_create(dma->rxbuf_dtag, 0, 2775 &dr->dr_spare_dmap); 2776 if (error) { 2777 device_printf(sc->sc_dev, 2778 "can't create RX buf DMA map\n"); 2779 goto out; /* XXX wrong! */ 2780 } 2781 2782 for (i = 0; i < dr->dr_numslots; i++) { 2783 dr->getdesc(dr, i, &desc, &mt); 2784 2785 error = bus_dmamap_create(dma->rxbuf_dtag, 0, 2786 &mt->mt_dmap); 2787 if (error) { 2788 device_printf(sc->sc_dev, 2789 "can't create RX buf DMA map\n"); 2790 goto out; /* XXX wrong! */ 2791 } 2792 error = bwn_dma_newbuf(dr, desc, mt, 1); 2793 if (error) { 2794 device_printf(sc->sc_dev, 2795 "failed to allocate RX buf\n"); 2796 goto out; /* XXX wrong! */ 2797 } 2798 } 2799 2800 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 2801 BUS_DMASYNC_PREWRITE); 2802 2803 dr->dr_usedslot = dr->dr_numslots; 2804 } 2805 2806 out: 2807 return (dr); 2808 2809fail2: 2810 if (dr->dr_txhdr_cache != NULL) { 2811 contigfree(dr->dr_txhdr_cache, 2812 (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * 2813 BWN_MAXTXHDRSIZE, M_DEVBUF); 2814 } 2815fail1: 2816 free(dr->dr_meta, M_DEVBUF); 2817fail0: 2818 free(dr, M_DEVBUF); 2819 return (NULL); 2820} 2821 2822static void 2823bwn_dma_ringfree(struct bwn_dma_ring **dr) 2824{ 2825 2826 if (dr == NULL) 2827 return; 2828 2829 bwn_dma_free_descbufs(*dr); 2830 bwn_dma_free_ringmemory(*dr); 2831 2832 if ((*dr)->dr_txhdr_cache != NULL) { 2833 contigfree((*dr)->dr_txhdr_cache, 2834 ((*dr)->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * 2835 BWN_MAXTXHDRSIZE, M_DEVBUF); 2836 } 2837 free((*dr)->dr_meta, M_DEVBUF); 2838 free(*dr, M_DEVBUF); 2839 2840 *dr = NULL; 2841} 2842 2843static void 2844bwn_dma_32_getdesc(struct bwn_dma_ring *dr, int slot, 2845 struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta) 2846{ 2847 struct bwn_dmadesc32 *desc; 2848 2849 *meta = &(dr->dr_meta[slot]); 2850 desc = dr->dr_ring_descbase; 2851 desc = &(desc[slot]); 2852 2853 *gdesc = (struct bwn_dmadesc_generic *)desc; 2854} 2855 2856static void 2857bwn_dma_32_setdesc(struct bwn_dma_ring *dr, 2858 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize, 2859 int start, int end, int irq) 2860{ 2861 struct bwn_dmadesc32 *descbase = dr->dr_ring_descbase; 2862 struct bwn_softc *sc = dr->dr_mac->mac_sc; 2863 uint32_t addr, addrext, ctl; 2864 int slot; 2865 2866 slot = (int)(&(desc->dma.dma32) - descbase); 2867 KASSERT(slot >= 0 && slot < dr->dr_numslots, 2868 ("%s:%d: fail", __func__, __LINE__)); 2869 2870 addr = (uint32_t) (dmaaddr & ~SIBA_DMA_TRANSLATION_MASK); 2871 addrext = (uint32_t) (dmaaddr & SIBA_DMA_TRANSLATION_MASK) >> 30; 2872 addr |= siba_dma_translation(sc->sc_dev); 2873 ctl = bufsize & BWN_DMA32_DCTL_BYTECNT; 2874 if (slot == dr->dr_numslots - 1) 2875 ctl |= BWN_DMA32_DCTL_DTABLEEND; 2876 if (start) 2877 ctl |= BWN_DMA32_DCTL_FRAMESTART; 2878 if (end) 2879 ctl |= BWN_DMA32_DCTL_FRAMEEND; 2880 if (irq) 2881 ctl |= BWN_DMA32_DCTL_IRQ; 2882 ctl |= (addrext << BWN_DMA32_DCTL_ADDREXT_SHIFT) 2883 & BWN_DMA32_DCTL_ADDREXT_MASK; 2884 2885 desc->dma.dma32.control = htole32(ctl); 2886 desc->dma.dma32.address = htole32(addr); 2887} 2888 2889static void 2890bwn_dma_32_start_transfer(struct bwn_dma_ring *dr, int slot) 2891{ 2892 2893 BWN_DMA_WRITE(dr, BWN_DMA32_TXINDEX, 2894 (uint32_t)(slot * sizeof(struct bwn_dmadesc32))); 2895} 2896 2897static void 2898bwn_dma_32_suspend(struct bwn_dma_ring *dr) 2899{ 2900 2901 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, 2902 BWN_DMA_READ(dr, BWN_DMA32_TXCTL) | BWN_DMA32_TXSUSPEND); 2903} 2904 2905static void 2906bwn_dma_32_resume(struct bwn_dma_ring *dr) 2907{ 2908 2909 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, 2910 BWN_DMA_READ(dr, BWN_DMA32_TXCTL) & ~BWN_DMA32_TXSUSPEND); 2911} 2912 2913static int 2914bwn_dma_32_get_curslot(struct bwn_dma_ring *dr) 2915{ 2916 uint32_t val; 2917 2918 val = BWN_DMA_READ(dr, BWN_DMA32_RXSTATUS); 2919 val &= BWN_DMA32_RXDPTR; 2920 2921 return (val / sizeof(struct bwn_dmadesc32)); 2922} 2923 2924static void 2925bwn_dma_32_set_curslot(struct bwn_dma_ring *dr, int slot) 2926{ 2927 2928 BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, 2929 (uint32_t) (slot * sizeof(struct bwn_dmadesc32))); 2930} 2931 2932static void 2933bwn_dma_64_getdesc(struct bwn_dma_ring *dr, int slot, 2934 struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta) 2935{ 2936 struct bwn_dmadesc64 *desc; 2937 2938 *meta = &(dr->dr_meta[slot]); 2939 desc = dr->dr_ring_descbase; 2940 desc = &(desc[slot]); 2941 2942 *gdesc = (struct bwn_dmadesc_generic *)desc; 2943} 2944 2945static void 2946bwn_dma_64_setdesc(struct bwn_dma_ring *dr, 2947 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize, 2948 int start, int end, int irq) 2949{ 2950 struct bwn_dmadesc64 *descbase = dr->dr_ring_descbase; 2951 struct bwn_softc *sc = dr->dr_mac->mac_sc; 2952 int slot; 2953 uint32_t ctl0 = 0, ctl1 = 0; 2954 uint32_t addrlo, addrhi; 2955 uint32_t addrext; 2956 2957 slot = (int)(&(desc->dma.dma64) - descbase); 2958 KASSERT(slot >= 0 && slot < dr->dr_numslots, 2959 ("%s:%d: fail", __func__, __LINE__)); 2960 2961 addrlo = (uint32_t) (dmaaddr & 0xffffffff); 2962 addrhi = (((uint64_t) dmaaddr >> 32) & ~SIBA_DMA_TRANSLATION_MASK); 2963 addrext = (((uint64_t) dmaaddr >> 32) & SIBA_DMA_TRANSLATION_MASK) >> 2964 30; 2965 addrhi |= (siba_dma_translation(sc->sc_dev) << 1); 2966 if (slot == dr->dr_numslots - 1) 2967 ctl0 |= BWN_DMA64_DCTL0_DTABLEEND; 2968 if (start) 2969 ctl0 |= BWN_DMA64_DCTL0_FRAMESTART; 2970 if (end) 2971 ctl0 |= BWN_DMA64_DCTL0_FRAMEEND; 2972 if (irq) 2973 ctl0 |= BWN_DMA64_DCTL0_IRQ; 2974 ctl1 |= bufsize & BWN_DMA64_DCTL1_BYTECNT; 2975 ctl1 |= (addrext << BWN_DMA64_DCTL1_ADDREXT_SHIFT) 2976 & BWN_DMA64_DCTL1_ADDREXT_MASK; 2977 2978 desc->dma.dma64.control0 = htole32(ctl0); 2979 desc->dma.dma64.control1 = htole32(ctl1); 2980 desc->dma.dma64.address_low = htole32(addrlo); 2981 desc->dma.dma64.address_high = htole32(addrhi); 2982} 2983 2984static void 2985bwn_dma_64_start_transfer(struct bwn_dma_ring *dr, int slot) 2986{ 2987 2988 BWN_DMA_WRITE(dr, BWN_DMA64_TXINDEX, 2989 (uint32_t)(slot * sizeof(struct bwn_dmadesc64))); 2990} 2991 2992static void 2993bwn_dma_64_suspend(struct bwn_dma_ring *dr) 2994{ 2995 2996 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, 2997 BWN_DMA_READ(dr, BWN_DMA64_TXCTL) | BWN_DMA64_TXSUSPEND); 2998} 2999 3000static void 3001bwn_dma_64_resume(struct bwn_dma_ring *dr) 3002{ 3003 3004 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, 3005 BWN_DMA_READ(dr, BWN_DMA64_TXCTL) & ~BWN_DMA64_TXSUSPEND); 3006} 3007 3008static int 3009bwn_dma_64_get_curslot(struct bwn_dma_ring *dr) 3010{ 3011 uint32_t val; 3012 3013 val = BWN_DMA_READ(dr, BWN_DMA64_RXSTATUS); 3014 val &= BWN_DMA64_RXSTATDPTR; 3015 3016 return (val / sizeof(struct bwn_dmadesc64)); 3017} 3018 3019static void 3020bwn_dma_64_set_curslot(struct bwn_dma_ring *dr, int slot) 3021{ 3022 3023 BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, 3024 (uint32_t)(slot * sizeof(struct bwn_dmadesc64))); 3025} 3026 3027static int 3028bwn_dma_allocringmemory(struct bwn_dma_ring *dr) 3029{ 3030 struct bwn_mac *mac = dr->dr_mac; 3031 struct bwn_dma *dma = &mac->mac_method.dma; 3032 struct bwn_softc *sc = mac->mac_sc; 3033 int error; 3034 3035 error = bus_dma_tag_create(dma->parent_dtag, 3036 BWN_ALIGN, 0, 3037 BUS_SPACE_MAXADDR, 3038 BUS_SPACE_MAXADDR, 3039 NULL, NULL, 3040 BWN_DMA_RINGMEMSIZE, 3041 1, 3042 BUS_SPACE_MAXSIZE_32BIT, 3043 0, 3044 NULL, NULL, 3045 &dr->dr_ring_dtag); 3046 if (error) { 3047 device_printf(sc->sc_dev, 3048 "can't create TX ring DMA tag: TODO frees\n"); 3049 return (-1); 3050 } 3051 3052 error = bus_dmamem_alloc(dr->dr_ring_dtag, 3053 &dr->dr_ring_descbase, BUS_DMA_WAITOK | BUS_DMA_ZERO, 3054 &dr->dr_ring_dmap); 3055 if (error) { 3056 device_printf(sc->sc_dev, 3057 "can't allocate DMA mem: TODO frees\n"); 3058 return (-1); 3059 } 3060 error = bus_dmamap_load(dr->dr_ring_dtag, dr->dr_ring_dmap, 3061 dr->dr_ring_descbase, BWN_DMA_RINGMEMSIZE, 3062 bwn_dma_ring_addr, &dr->dr_ring_dmabase, BUS_DMA_NOWAIT); 3063 if (error) { 3064 device_printf(sc->sc_dev, 3065 "can't load DMA mem: TODO free\n"); 3066 return (-1); 3067 } 3068 3069 return (0); 3070} 3071 3072static void 3073bwn_dma_setup(struct bwn_dma_ring *dr) 3074{ 3075 struct bwn_softc *sc = dr->dr_mac->mac_sc; 3076 uint64_t ring64; 3077 uint32_t addrext, ring32, value; 3078 uint32_t trans = siba_dma_translation(sc->sc_dev); 3079 3080 if (dr->dr_tx) { 3081 dr->dr_curslot = -1; 3082 3083 if (dr->dr_type == BWN_DMA_64BIT) { 3084 ring64 = (uint64_t)(dr->dr_ring_dmabase); 3085 addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK) 3086 >> 30; 3087 value = BWN_DMA64_TXENABLE; 3088 value |= (addrext << BWN_DMA64_TXADDREXT_SHIFT) 3089 & BWN_DMA64_TXADDREXT_MASK; 3090 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, value); 3091 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, 3092 (ring64 & 0xffffffff)); 3093 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, 3094 ((ring64 >> 32) & 3095 ~SIBA_DMA_TRANSLATION_MASK) | (trans << 1)); 3096 } else { 3097 ring32 = (uint32_t)(dr->dr_ring_dmabase); 3098 addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30; 3099 value = BWN_DMA32_TXENABLE; 3100 value |= (addrext << BWN_DMA32_TXADDREXT_SHIFT) 3101 & BWN_DMA32_TXADDREXT_MASK; 3102 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, value); 3103 BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, 3104 (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans); 3105 } 3106 return; 3107 } 3108 3109 /* 3110 * set for RX 3111 */ 3112 dr->dr_usedslot = dr->dr_numslots; 3113 3114 if (dr->dr_type == BWN_DMA_64BIT) { 3115 ring64 = (uint64_t)(dr->dr_ring_dmabase); 3116 addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK) >> 30; 3117 value = (dr->dr_frameoffset << BWN_DMA64_RXFROFF_SHIFT); 3118 value |= BWN_DMA64_RXENABLE; 3119 value |= (addrext << BWN_DMA64_RXADDREXT_SHIFT) 3120 & BWN_DMA64_RXADDREXT_MASK; 3121 BWN_DMA_WRITE(dr, BWN_DMA64_RXCTL, value); 3122 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, (ring64 & 0xffffffff)); 3123 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, 3124 ((ring64 >> 32) & ~SIBA_DMA_TRANSLATION_MASK) 3125 | (trans << 1)); 3126 BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, dr->dr_numslots * 3127 sizeof(struct bwn_dmadesc64)); 3128 } else { 3129 ring32 = (uint32_t)(dr->dr_ring_dmabase); 3130 addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30; 3131 value = (dr->dr_frameoffset << BWN_DMA32_RXFROFF_SHIFT); 3132 value |= BWN_DMA32_RXENABLE; 3133 value |= (addrext << BWN_DMA32_RXADDREXT_SHIFT) 3134 & BWN_DMA32_RXADDREXT_MASK; 3135 BWN_DMA_WRITE(dr, BWN_DMA32_RXCTL, value); 3136 BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, 3137 (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans); 3138 BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, dr->dr_numslots * 3139 sizeof(struct bwn_dmadesc32)); 3140 } 3141} 3142 3143static void 3144bwn_dma_free_ringmemory(struct bwn_dma_ring *dr) 3145{ 3146 3147 bus_dmamap_unload(dr->dr_ring_dtag, dr->dr_ring_dmap); 3148 bus_dmamem_free(dr->dr_ring_dtag, dr->dr_ring_descbase, 3149 dr->dr_ring_dmap); 3150} 3151 3152static void 3153bwn_dma_cleanup(struct bwn_dma_ring *dr) 3154{ 3155 3156 if (dr->dr_tx) { 3157 bwn_dma_tx_reset(dr->dr_mac, dr->dr_base, dr->dr_type); 3158 if (dr->dr_type == BWN_DMA_64BIT) { 3159 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, 0); 3160 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, 0); 3161 } else 3162 BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, 0); 3163 } else { 3164 bwn_dma_rx_reset(dr->dr_mac, dr->dr_base, dr->dr_type); 3165 if (dr->dr_type == BWN_DMA_64BIT) { 3166 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, 0); 3167 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, 0); 3168 } else 3169 BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, 0); 3170 } 3171} 3172 3173static void 3174bwn_dma_free_descbufs(struct bwn_dma_ring *dr) 3175{ 3176 struct bwn_dmadesc_generic *desc; 3177 struct bwn_dmadesc_meta *meta; 3178 struct bwn_mac *mac = dr->dr_mac; 3179 struct bwn_dma *dma = &mac->mac_method.dma; 3180 struct bwn_softc *sc = mac->mac_sc; 3181 int i; 3182 3183 if (!dr->dr_usedslot) 3184 return; 3185 for (i = 0; i < dr->dr_numslots; i++) { 3186 dr->getdesc(dr, i, &desc, &meta); 3187 3188 if (meta->mt_m == NULL) { 3189 if (!dr->dr_tx) 3190 device_printf(sc->sc_dev, "%s: not TX?\n", 3191 __func__); 3192 continue; 3193 } 3194 if (dr->dr_tx) { 3195 if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER) 3196 bus_dmamap_unload(dr->dr_txring_dtag, 3197 meta->mt_dmap); 3198 else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY) 3199 bus_dmamap_unload(dma->txbuf_dtag, 3200 meta->mt_dmap); 3201 } else 3202 bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap); 3203 bwn_dma_free_descbuf(dr, meta); 3204 } 3205} 3206 3207static int 3208bwn_dma_tx_reset(struct bwn_mac *mac, uint16_t base, 3209 int type) 3210{ 3211 struct bwn_softc *sc = mac->mac_sc; 3212 uint32_t value; 3213 int i; 3214 uint16_t offset; 3215 3216 for (i = 0; i < 10; i++) { 3217 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS : 3218 BWN_DMA32_TXSTATUS; 3219 value = BWN_READ_4(mac, base + offset); 3220 if (type == BWN_DMA_64BIT) { 3221 value &= BWN_DMA64_TXSTAT; 3222 if (value == BWN_DMA64_TXSTAT_DISABLED || 3223 value == BWN_DMA64_TXSTAT_IDLEWAIT || 3224 value == BWN_DMA64_TXSTAT_STOPPED) 3225 break; 3226 } else { 3227 value &= BWN_DMA32_TXSTATE; 3228 if (value == BWN_DMA32_TXSTAT_DISABLED || 3229 value == BWN_DMA32_TXSTAT_IDLEWAIT || 3230 value == BWN_DMA32_TXSTAT_STOPPED) 3231 break; 3232 } 3233 DELAY(1000); 3234 } 3235 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXCTL : BWN_DMA32_TXCTL; 3236 BWN_WRITE_4(mac, base + offset, 0); 3237 for (i = 0; i < 10; i++) { 3238 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS : 3239 BWN_DMA32_TXSTATUS; 3240 value = BWN_READ_4(mac, base + offset); 3241 if (type == BWN_DMA_64BIT) { 3242 value &= BWN_DMA64_TXSTAT; 3243 if (value == BWN_DMA64_TXSTAT_DISABLED) { 3244 i = -1; 3245 break; 3246 } 3247 } else { 3248 value &= BWN_DMA32_TXSTATE; 3249 if (value == BWN_DMA32_TXSTAT_DISABLED) { 3250 i = -1; 3251 break; 3252 } 3253 } 3254 DELAY(1000); 3255 } 3256 if (i != -1) { 3257 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 3258 return (ENODEV); 3259 } 3260 DELAY(1000); 3261 3262 return (0); 3263} 3264 3265static int 3266bwn_dma_rx_reset(struct bwn_mac *mac, uint16_t base, 3267 int type) 3268{ 3269 struct bwn_softc *sc = mac->mac_sc; 3270 uint32_t value; 3271 int i; 3272 uint16_t offset; 3273 3274 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXCTL : BWN_DMA32_RXCTL; 3275 BWN_WRITE_4(mac, base + offset, 0); 3276 for (i = 0; i < 10; i++) { 3277 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXSTATUS : 3278 BWN_DMA32_RXSTATUS; 3279 value = BWN_READ_4(mac, base + offset); 3280 if (type == BWN_DMA_64BIT) { 3281 value &= BWN_DMA64_RXSTAT; 3282 if (value == BWN_DMA64_RXSTAT_DISABLED) { 3283 i = -1; 3284 break; 3285 } 3286 } else { 3287 value &= BWN_DMA32_RXSTATE; 3288 if (value == BWN_DMA32_RXSTAT_DISABLED) { 3289 i = -1; 3290 break; 3291 } 3292 } 3293 DELAY(1000); 3294 } 3295 if (i != -1) { 3296 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 3297 return (ENODEV); 3298 } 3299 3300 return (0); 3301} 3302 3303static void 3304bwn_dma_free_descbuf(struct bwn_dma_ring *dr, 3305 struct bwn_dmadesc_meta *meta) 3306{ 3307 3308 if (meta->mt_m != NULL) { 3309 m_freem(meta->mt_m); 3310 meta->mt_m = NULL; 3311 } 3312 if (meta->mt_ni != NULL) { 3313 ieee80211_free_node(meta->mt_ni); 3314 meta->mt_ni = NULL; 3315 } 3316} 3317 3318static void 3319bwn_dma_set_redzone(struct bwn_dma_ring *dr, struct mbuf *m) 3320{ 3321 struct bwn_rxhdr4 *rxhdr; 3322 unsigned char *frame; 3323 3324 rxhdr = mtod(m, struct bwn_rxhdr4 *); 3325 rxhdr->frame_len = 0; 3326 3327 KASSERT(dr->dr_rx_bufsize >= dr->dr_frameoffset + 3328 sizeof(struct bwn_plcp6) + 2, 3329 ("%s:%d: fail", __func__, __LINE__)); 3330 frame = mtod(m, char *) + dr->dr_frameoffset; 3331 memset(frame, 0xff, sizeof(struct bwn_plcp6) + 2 /* padding */); 3332} 3333 3334static uint8_t 3335bwn_dma_check_redzone(struct bwn_dma_ring *dr, struct mbuf *m) 3336{ 3337 unsigned char *f = mtod(m, char *) + dr->dr_frameoffset; 3338 3339 return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) 3340 == 0xff); 3341} 3342 3343static void 3344bwn_wme_init(struct bwn_mac *mac) 3345{ 3346 3347 bwn_wme_load(mac); 3348 3349 /* enable WME support. */ 3350 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_EDCF); 3351 BWN_WRITE_2(mac, BWN_IFSCTL, BWN_READ_2(mac, BWN_IFSCTL) | 3352 BWN_IFSCTL_USE_EDCF); 3353} 3354 3355static void 3356bwn_spu_setdelay(struct bwn_mac *mac, int idle) 3357{ 3358 struct bwn_softc *sc = mac->mac_sc; 3359 struct ieee80211com *ic = &sc->sc_ic; 3360 uint16_t delay; /* microsec */ 3361 3362 delay = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 3700 : 1050; 3363 if (ic->ic_opmode == IEEE80211_M_IBSS || idle) 3364 delay = 500; 3365 if ((mac->mac_phy.rf_ver == 0x2050) && (mac->mac_phy.rf_rev == 8)) 3366 delay = max(delay, (uint16_t)2400); 3367 3368 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SPU_WAKEUP, delay); 3369} 3370 3371static void 3372bwn_bt_enable(struct bwn_mac *mac) 3373{ 3374 struct bwn_softc *sc = mac->mac_sc; 3375 uint64_t hf; 3376 3377 if (bwn_bluetooth == 0) 3378 return; 3379 if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCOEXIST) == 0) 3380 return; 3381 if (mac->mac_phy.type != BWN_PHYTYPE_B && !mac->mac_phy.gmode) 3382 return; 3383 3384 hf = bwn_hf_read(mac); 3385 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCMOD) 3386 hf |= BWN_HF_BT_COEXISTALT; 3387 else 3388 hf |= BWN_HF_BT_COEXIST; 3389 bwn_hf_write(mac, hf); 3390} 3391 3392static void 3393bwn_set_macaddr(struct bwn_mac *mac) 3394{ 3395 3396 bwn_mac_write_bssid(mac); 3397 bwn_mac_setfilter(mac, BWN_MACFILTER_SELF, 3398 mac->mac_sc->sc_ic.ic_macaddr); 3399} 3400 3401static void 3402bwn_clear_keys(struct bwn_mac *mac) 3403{ 3404 int i; 3405 3406 for (i = 0; i < mac->mac_max_nr_keys; i++) { 3407 KASSERT(i >= 0 && i < mac->mac_max_nr_keys, 3408 ("%s:%d: fail", __func__, __LINE__)); 3409 3410 bwn_key_dowrite(mac, i, BWN_SEC_ALGO_NONE, 3411 NULL, BWN_SEC_KEYSIZE, NULL); 3412 if ((i <= 3) && !BWN_SEC_NEWAPI(mac)) { 3413 bwn_key_dowrite(mac, i + 4, BWN_SEC_ALGO_NONE, 3414 NULL, BWN_SEC_KEYSIZE, NULL); 3415 } 3416 mac->mac_key[i].keyconf = NULL; 3417 } 3418} 3419 3420static void 3421bwn_crypt_init(struct bwn_mac *mac) 3422{ 3423 struct bwn_softc *sc = mac->mac_sc; 3424 3425 mac->mac_max_nr_keys = (siba_get_revid(sc->sc_dev) >= 5) ? 58 : 20; 3426 KASSERT(mac->mac_max_nr_keys <= N(mac->mac_key), 3427 ("%s:%d: fail", __func__, __LINE__)); 3428 mac->mac_ktp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_KEY_TABLEP); 3429 mac->mac_ktp *= 2; 3430 if (siba_get_revid(sc->sc_dev) >= 5) 3431 BWN_WRITE_2(mac, BWN_RCMTA_COUNT, mac->mac_max_nr_keys - 8); 3432 bwn_clear_keys(mac); 3433} 3434 3435static void 3436bwn_chip_exit(struct bwn_mac *mac) 3437{ 3438 struct bwn_softc *sc = mac->mac_sc; 3439 3440 bwn_phy_exit(mac); 3441 siba_gpio_set(sc->sc_dev, 0); 3442} 3443 3444static int 3445bwn_fw_fillinfo(struct bwn_mac *mac) 3446{ 3447 int error; 3448 3449 error = bwn_fw_gets(mac, BWN_FWTYPE_DEFAULT); 3450 if (error == 0) 3451 return (0); 3452 error = bwn_fw_gets(mac, BWN_FWTYPE_OPENSOURCE); 3453 if (error == 0) 3454 return (0); 3455 return (error); 3456} 3457 3458static int 3459bwn_gpio_init(struct bwn_mac *mac) 3460{ 3461 struct bwn_softc *sc = mac->mac_sc; 3462 uint32_t mask = 0x1f, set = 0xf, value; 3463 3464 BWN_WRITE_4(mac, BWN_MACCTL, 3465 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GPOUT_MASK); 3466 BWN_WRITE_2(mac, BWN_GPIO_MASK, 3467 BWN_READ_2(mac, BWN_GPIO_MASK) | 0x000f); 3468 3469 if (siba_get_chipid(sc->sc_dev) == 0x4301) { 3470 mask |= 0x0060; 3471 set |= 0x0060; 3472 } 3473 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL) { 3474 BWN_WRITE_2(mac, BWN_GPIO_MASK, 3475 BWN_READ_2(mac, BWN_GPIO_MASK) | 0x0200); 3476 mask |= 0x0200; 3477 set |= 0x0200; 3478 } 3479 if (siba_get_revid(sc->sc_dev) >= 2) 3480 mask |= 0x0010; 3481 3482 value = siba_gpio_get(sc->sc_dev); 3483 if (value == -1) 3484 return (0); 3485 siba_gpio_set(sc->sc_dev, (value & mask) | set); 3486 3487 return (0); 3488} 3489 3490static int 3491bwn_fw_loadinitvals(struct bwn_mac *mac) 3492{ 3493#define GETFWOFFSET(fwp, offset) \ 3494 ((const struct bwn_fwinitvals *)((const char *)fwp.fw->data + offset)) 3495 const size_t hdr_len = sizeof(struct bwn_fwhdr); 3496 const struct bwn_fwhdr *hdr; 3497 struct bwn_fw *fw = &mac->mac_fw; 3498 int error; 3499 3500 hdr = (const struct bwn_fwhdr *)(fw->initvals.fw->data); 3501 error = bwn_fwinitvals_write(mac, GETFWOFFSET(fw->initvals, hdr_len), 3502 be32toh(hdr->size), fw->initvals.fw->datasize - hdr_len); 3503 if (error) 3504 return (error); 3505 if (fw->initvals_band.fw) { 3506 hdr = (const struct bwn_fwhdr *)(fw->initvals_band.fw->data); 3507 error = bwn_fwinitvals_write(mac, 3508 GETFWOFFSET(fw->initvals_band, hdr_len), 3509 be32toh(hdr->size), 3510 fw->initvals_band.fw->datasize - hdr_len); 3511 } 3512 return (error); 3513#undef GETFWOFFSET 3514} 3515 3516static int 3517bwn_phy_init(struct bwn_mac *mac) 3518{ 3519 struct bwn_softc *sc = mac->mac_sc; 3520 int error; 3521 3522 mac->mac_phy.chan = mac->mac_phy.get_default_chan(mac); 3523 mac->mac_phy.rf_onoff(mac, 1); 3524 error = mac->mac_phy.init(mac); 3525 if (error) { 3526 device_printf(sc->sc_dev, "PHY init failed\n"); 3527 goto fail0; 3528 } 3529 error = bwn_switch_channel(mac, 3530 mac->mac_phy.get_default_chan(mac)); 3531 if (error) { 3532 device_printf(sc->sc_dev, 3533 "failed to switch default channel\n"); 3534 goto fail1; 3535 } 3536 return (0); 3537fail1: 3538 if (mac->mac_phy.exit) 3539 mac->mac_phy.exit(mac); 3540fail0: 3541 mac->mac_phy.rf_onoff(mac, 0); 3542 3543 return (error); 3544} 3545 3546static void 3547bwn_set_txantenna(struct bwn_mac *mac, int antenna) 3548{ 3549 uint16_t ant; 3550 uint16_t tmp; 3551 3552 ant = bwn_ant2phy(antenna); 3553 3554 /* For ACK/CTS */ 3555 tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL); 3556 tmp = (tmp & ~BWN_TX_PHY_ANT) | ant; 3557 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, tmp); 3558 /* For Probe Resposes */ 3559 tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL); 3560 tmp = (tmp & ~BWN_TX_PHY_ANT) | ant; 3561 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, tmp); 3562} 3563 3564static void 3565bwn_set_opmode(struct bwn_mac *mac) 3566{ 3567 struct bwn_softc *sc = mac->mac_sc; 3568 struct ieee80211com *ic = &sc->sc_ic; 3569 uint32_t ctl; 3570 uint16_t cfp_pretbtt; 3571 3572 ctl = BWN_READ_4(mac, BWN_MACCTL); 3573 ctl &= ~(BWN_MACCTL_HOSTAP | BWN_MACCTL_PASS_CTL | 3574 BWN_MACCTL_PASS_BADPLCP | BWN_MACCTL_PASS_BADFCS | 3575 BWN_MACCTL_PROMISC | BWN_MACCTL_BEACON_PROMISC); 3576 ctl |= BWN_MACCTL_STA; 3577 3578 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3579 ic->ic_opmode == IEEE80211_M_MBSS) 3580 ctl |= BWN_MACCTL_HOSTAP; 3581 else if (ic->ic_opmode == IEEE80211_M_IBSS) 3582 ctl &= ~BWN_MACCTL_STA; 3583 ctl |= sc->sc_filters; 3584 3585 if (siba_get_revid(sc->sc_dev) <= 4) 3586 ctl |= BWN_MACCTL_PROMISC; 3587 3588 BWN_WRITE_4(mac, BWN_MACCTL, ctl); 3589 3590 cfp_pretbtt = 2; 3591 if ((ctl & BWN_MACCTL_STA) && !(ctl & BWN_MACCTL_HOSTAP)) { 3592 if (siba_get_chipid(sc->sc_dev) == 0x4306 && 3593 siba_get_chiprev(sc->sc_dev) == 3) 3594 cfp_pretbtt = 100; 3595 else 3596 cfp_pretbtt = 50; 3597 } 3598 BWN_WRITE_2(mac, 0x612, cfp_pretbtt); 3599} 3600 3601static int 3602bwn_dma_gettype(struct bwn_mac *mac) 3603{ 3604 uint32_t tmp; 3605 uint16_t base; 3606 3607 tmp = BWN_READ_4(mac, SIBA_TGSHIGH); 3608 if (tmp & SIBA_TGSHIGH_DMA64) 3609 return (BWN_DMA_64BIT); 3610 base = bwn_dma_base(0, 0); 3611 BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK); 3612 tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL); 3613 if (tmp & BWN_DMA32_TXADDREXT_MASK) 3614 return (BWN_DMA_32BIT); 3615 3616 return (BWN_DMA_30BIT); 3617} 3618 3619static void 3620bwn_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 3621{ 3622 if (!error) { 3623 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 3624 *((bus_addr_t *)arg) = seg->ds_addr; 3625 } 3626} 3627 3628void 3629bwn_dummy_transmission(struct bwn_mac *mac, int ofdm, int paon) 3630{ 3631 struct bwn_phy *phy = &mac->mac_phy; 3632 struct bwn_softc *sc = mac->mac_sc; 3633 unsigned int i, max_loop; 3634 uint16_t value; 3635 uint32_t buffer[5] = { 3636 0x00000000, 0x00d40000, 0x00000000, 0x01000000, 0x00000000 3637 }; 3638 3639 if (ofdm) { 3640 max_loop = 0x1e; 3641 buffer[0] = 0x000201cc; 3642 } else { 3643 max_loop = 0xfa; 3644 buffer[0] = 0x000b846e; 3645 } 3646 3647 BWN_ASSERT_LOCKED(mac->mac_sc); 3648 3649 for (i = 0; i < 5; i++) 3650 bwn_ram_write(mac, i * 4, buffer[i]); 3651 3652 BWN_WRITE_2(mac, 0x0568, 0x0000); 3653 BWN_WRITE_2(mac, 0x07c0, 3654 (siba_get_revid(sc->sc_dev) < 11) ? 0x0000 : 0x0100); 3655 3656 value = (ofdm ? 0x41 : 0x40); 3657 BWN_WRITE_2(mac, 0x050c, value); 3658 3659 if (phy->type == BWN_PHYTYPE_N || phy->type == BWN_PHYTYPE_LP || 3660 phy->type == BWN_PHYTYPE_LCN) 3661 BWN_WRITE_2(mac, 0x0514, 0x1a02); 3662 BWN_WRITE_2(mac, 0x0508, 0x0000); 3663 BWN_WRITE_2(mac, 0x050a, 0x0000); 3664 BWN_WRITE_2(mac, 0x054c, 0x0000); 3665 BWN_WRITE_2(mac, 0x056a, 0x0014); 3666 BWN_WRITE_2(mac, 0x0568, 0x0826); 3667 BWN_WRITE_2(mac, 0x0500, 0x0000); 3668 3669 /* XXX TODO: n phy pa override? */ 3670 3671 switch (phy->type) { 3672 case BWN_PHYTYPE_N: 3673 case BWN_PHYTYPE_LCN: 3674 BWN_WRITE_2(mac, 0x0502, 0x00d0); 3675 break; 3676 case BWN_PHYTYPE_LP: 3677 BWN_WRITE_2(mac, 0x0502, 0x0050); 3678 break; 3679 default: 3680 BWN_WRITE_2(mac, 0x0502, 0x0030); 3681 break; 3682 } 3683 3684 /* flush */ 3685 BWN_READ_2(mac, 0x0502); 3686 3687 if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5) 3688 BWN_RF_WRITE(mac, 0x0051, 0x0017); 3689 for (i = 0x00; i < max_loop; i++) { 3690 value = BWN_READ_2(mac, 0x050e); 3691 if (value & 0x0080) 3692 break; 3693 DELAY(10); 3694 } 3695 for (i = 0x00; i < 0x0a; i++) { 3696 value = BWN_READ_2(mac, 0x050e); 3697 if (value & 0x0400) 3698 break; 3699 DELAY(10); 3700 } 3701 for (i = 0x00; i < 0x19; i++) { 3702 value = BWN_READ_2(mac, 0x0690); 3703 if (!(value & 0x0100)) 3704 break; 3705 DELAY(10); 3706 } 3707 if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5) 3708 BWN_RF_WRITE(mac, 0x0051, 0x0037); 3709} 3710 3711void 3712bwn_ram_write(struct bwn_mac *mac, uint16_t offset, uint32_t val) 3713{ 3714 uint32_t macctl; 3715 3716 KASSERT(offset % 4 == 0, ("%s:%d: fail", __func__, __LINE__)); 3717 3718 macctl = BWN_READ_4(mac, BWN_MACCTL); 3719 if (macctl & BWN_MACCTL_BIGENDIAN) 3720 printf("TODO: need swap\n"); 3721 3722 BWN_WRITE_4(mac, BWN_RAM_CONTROL, offset); 3723 BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE); 3724 BWN_WRITE_4(mac, BWN_RAM_DATA, val); 3725} 3726 3727void 3728bwn_mac_suspend(struct bwn_mac *mac) 3729{ 3730 struct bwn_softc *sc = mac->mac_sc; 3731 int i; 3732 uint32_t tmp; 3733 3734 KASSERT(mac->mac_suspended >= 0, 3735 ("%s:%d: fail", __func__, __LINE__)); 3736 3737 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n", 3738 __func__, mac->mac_suspended); 3739 3740 if (mac->mac_suspended == 0) { 3741 bwn_psctl(mac, BWN_PS_AWAKE); 3742 BWN_WRITE_4(mac, BWN_MACCTL, 3743 BWN_READ_4(mac, BWN_MACCTL) 3744 & ~BWN_MACCTL_ON); 3745 BWN_READ_4(mac, BWN_MACCTL); 3746 for (i = 35; i; i--) { 3747 tmp = BWN_READ_4(mac, BWN_INTR_REASON); 3748 if (tmp & BWN_INTR_MAC_SUSPENDED) 3749 goto out; 3750 DELAY(10); 3751 } 3752 for (i = 40; i; i--) { 3753 tmp = BWN_READ_4(mac, BWN_INTR_REASON); 3754 if (tmp & BWN_INTR_MAC_SUSPENDED) 3755 goto out; 3756 DELAY(1000); 3757 } 3758 device_printf(sc->sc_dev, "MAC suspend failed\n"); 3759 } 3760out: 3761 mac->mac_suspended++; 3762} 3763 3764void 3765bwn_mac_enable(struct bwn_mac *mac) 3766{ 3767 struct bwn_softc *sc = mac->mac_sc; 3768 uint16_t state; 3769 3770 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n", 3771 __func__, mac->mac_suspended); 3772 3773 state = bwn_shm_read_2(mac, BWN_SHARED, 3774 BWN_SHARED_UCODESTAT); 3775 if (state != BWN_SHARED_UCODESTAT_SUSPEND && 3776 state != BWN_SHARED_UCODESTAT_SLEEP) { 3777 DPRINTF(sc, BWN_DEBUG_FW, 3778 "%s: warn: firmware state (%d)\n", 3779 __func__, state); 3780 } 3781 3782 mac->mac_suspended--; 3783 KASSERT(mac->mac_suspended >= 0, 3784 ("%s:%d: fail", __func__, __LINE__)); 3785 if (mac->mac_suspended == 0) { 3786 BWN_WRITE_4(mac, BWN_MACCTL, 3787 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_ON); 3788 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_MAC_SUSPENDED); 3789 BWN_READ_4(mac, BWN_MACCTL); 3790 BWN_READ_4(mac, BWN_INTR_REASON); 3791 bwn_psctl(mac, 0); 3792 } 3793} 3794 3795void 3796bwn_psctl(struct bwn_mac *mac, uint32_t flags) 3797{ 3798 struct bwn_softc *sc = mac->mac_sc; 3799 int i; 3800 uint16_t ucstat; 3801 3802 KASSERT(!((flags & BWN_PS_ON) && (flags & BWN_PS_OFF)), 3803 ("%s:%d: fail", __func__, __LINE__)); 3804 KASSERT(!((flags & BWN_PS_AWAKE) && (flags & BWN_PS_ASLEEP)), 3805 ("%s:%d: fail", __func__, __LINE__)); 3806 3807 /* XXX forcibly awake and hwps-off */ 3808 3809 BWN_WRITE_4(mac, BWN_MACCTL, 3810 (BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_AWAKE) & 3811 ~BWN_MACCTL_HWPS); 3812 BWN_READ_4(mac, BWN_MACCTL); 3813 if (siba_get_revid(sc->sc_dev) >= 5) { 3814 for (i = 0; i < 100; i++) { 3815 ucstat = bwn_shm_read_2(mac, BWN_SHARED, 3816 BWN_SHARED_UCODESTAT); 3817 if (ucstat != BWN_SHARED_UCODESTAT_SLEEP) 3818 break; 3819 DELAY(10); 3820 } 3821 } 3822 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: ucstat=%d\n", __func__, 3823 ucstat); 3824} 3825 3826static int 3827bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type) 3828{ 3829 struct bwn_softc *sc = mac->mac_sc; 3830 struct bwn_fw *fw = &mac->mac_fw; 3831 const uint8_t rev = siba_get_revid(sc->sc_dev); 3832 const char *filename; 3833 uint32_t high; 3834 int error; 3835 3836 /* microcode */ 3837 filename = NULL; 3838 switch (rev) { 3839 case 42: 3840 if (mac->mac_phy.type == BWN_PHYTYPE_AC) 3841 filename = "ucode42"; 3842 break; 3843 case 40: 3844 if (mac->mac_phy.type == BWN_PHYTYPE_AC) 3845 filename = "ucode40"; 3846 break; 3847 case 33: 3848 if (mac->mac_phy.type == BWN_PHYTYPE_LCN40) 3849 filename = "ucode33_lcn40"; 3850 break; 3851 case 30: 3852 if (mac->mac_phy.type == BWN_PHYTYPE_N) 3853 filename = "ucode30_mimo"; 3854 break; 3855 case 29: 3856 if (mac->mac_phy.type == BWN_PHYTYPE_HT) 3857 filename = "ucode29_mimo"; 3858 break; 3859 case 26: 3860 if (mac->mac_phy.type == BWN_PHYTYPE_HT) 3861 filename = "ucode26_mimo"; 3862 break; 3863 case 28: 3864 case 25: 3865 if (mac->mac_phy.type == BWN_PHYTYPE_N) 3866 filename = "ucode25_mimo"; 3867 else if (mac->mac_phy.type == BWN_PHYTYPE_LCN) 3868 filename = "ucode25_lcn"; 3869 break; 3870 case 24: 3871 if (mac->mac_phy.type == BWN_PHYTYPE_LCN) 3872 filename = "ucode24_lcn"; 3873 break; 3874 case 23: 3875 if (mac->mac_phy.type == BWN_PHYTYPE_N) 3876 filename = "ucode16_mimo"; 3877 break; 3878 case 16: 3879 case 17: 3880 case 18: 3881 case 19: 3882 if (mac->mac_phy.type == BWN_PHYTYPE_N) 3883 filename = "ucode16_mimo"; 3884 else if (mac->mac_phy.type == BWN_PHYTYPE_LP) 3885 filename = "ucode16_lp"; 3886 break; 3887 case 15: 3888 filename = "ucode15"; 3889 break; 3890 case 14: 3891 filename = "ucode14"; 3892 break; 3893 case 13: 3894 filename = "ucode13"; 3895 break; 3896 case 12: 3897 case 11: 3898 filename = "ucode11"; 3899 break; 3900 case 10: 3901 case 9: 3902 case 8: 3903 case 7: 3904 case 6: 3905 case 5: 3906 filename = "ucode5"; 3907 break; 3908 default: 3909 device_printf(sc->sc_dev, "no ucode for rev %d\n", rev); 3910 bwn_release_firmware(mac); 3911 return (EOPNOTSUPP); 3912 } 3913 3914 device_printf(sc->sc_dev, "ucode fw: %s\n", filename); 3915 error = bwn_fw_get(mac, type, filename, &fw->ucode); 3916 if (error) { 3917 bwn_release_firmware(mac); 3918 return (error); 3919 } 3920 3921 /* PCM */ 3922 KASSERT(fw->no_pcmfile == 0, ("%s:%d fail", __func__, __LINE__)); 3923 if (rev >= 5 && rev <= 10) { 3924 error = bwn_fw_get(mac, type, "pcm5", &fw->pcm); 3925 if (error == ENOENT) 3926 fw->no_pcmfile = 1; 3927 else if (error) { 3928 bwn_release_firmware(mac); 3929 return (error); 3930 } 3931 } else if (rev < 11) { 3932 device_printf(sc->sc_dev, "no PCM for rev %d\n", rev); 3933 bwn_release_firmware(mac); 3934 return (EOPNOTSUPP); 3935 } 3936 3937 /* initvals */ 3938 high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH); 3939 switch (mac->mac_phy.type) { 3940 case BWN_PHYTYPE_A: 3941 if (rev < 5 || rev > 10) 3942 goto fail1; 3943 if (high & BWN_TGSHIGH_HAVE_2GHZ) 3944 filename = "a0g1initvals5"; 3945 else 3946 filename = "a0g0initvals5"; 3947 break; 3948 case BWN_PHYTYPE_G: 3949 if (rev >= 5 && rev <= 10) 3950 filename = "b0g0initvals5"; 3951 else if (rev >= 13) 3952 filename = "b0g0initvals13"; 3953 else 3954 goto fail1; 3955 break; 3956 case BWN_PHYTYPE_LP: 3957 if (rev == 13) 3958 filename = "lp0initvals13"; 3959 else if (rev == 14) 3960 filename = "lp0initvals14"; 3961 else if (rev >= 15) 3962 filename = "lp0initvals15"; 3963 else 3964 goto fail1; 3965 break; 3966 case BWN_PHYTYPE_N: 3967 if (rev == 30) 3968 filename = "n16initvals30"; 3969 else if (rev == 28 || rev == 25) 3970 filename = "n0initvals25"; 3971 else if (rev == 24) 3972 filename = "n0initvals24"; 3973 else if (rev == 23) 3974 filename = "n0initvals16"; 3975 else if (rev >= 16 && rev <= 18) 3976 filename = "n0initvals16"; 3977 else if (rev >= 11 && rev <= 12) 3978 filename = "n0initvals11"; 3979 else 3980 goto fail1; 3981 break; 3982 default: 3983 goto fail1; 3984 } 3985 error = bwn_fw_get(mac, type, filename, &fw->initvals); 3986 if (error) { 3987 bwn_release_firmware(mac); 3988 return (error); 3989 } 3990 3991 /* bandswitch initvals */ 3992 switch (mac->mac_phy.type) { 3993 case BWN_PHYTYPE_A: 3994 if (rev >= 5 && rev <= 10) { 3995 if (high & BWN_TGSHIGH_HAVE_2GHZ) 3996 filename = "a0g1bsinitvals5"; 3997 else 3998 filename = "a0g0bsinitvals5"; 3999 } else if (rev >= 11) 4000 filename = NULL; 4001 else 4002 goto fail1; 4003 break; 4004 case BWN_PHYTYPE_G: 4005 if (rev >= 5 && rev <= 10) 4006 filename = "b0g0bsinitvals5"; 4007 else if (rev >= 11) 4008 filename = NULL; 4009 else 4010 goto fail1; 4011 break; 4012 case BWN_PHYTYPE_LP: 4013 if (rev == 13) 4014 filename = "lp0bsinitvals13"; 4015 else if (rev == 14) 4016 filename = "lp0bsinitvals14"; 4017 else if (rev >= 15) 4018 filename = "lp0bsinitvals15"; 4019 else 4020 goto fail1; 4021 break; 4022 case BWN_PHYTYPE_N: 4023 if (rev == 30) 4024 filename = "n16bsinitvals30"; 4025 else if (rev == 28 || rev == 25) 4026 filename = "n0bsinitvals25"; 4027 else if (rev == 24) 4028 filename = "n0bsinitvals24"; 4029 else if (rev == 23) 4030 filename = "n0bsinitvals16"; 4031 else if (rev >= 16 && rev <= 18) 4032 filename = "n0bsinitvals16"; 4033 else if (rev >= 11 && rev <= 12) 4034 filename = "n0bsinitvals11"; 4035 else 4036 goto fail1; 4037 break; 4038 default: 4039 device_printf(sc->sc_dev, "unknown phy (%d)\n", 4040 mac->mac_phy.type); 4041 goto fail1; 4042 } 4043 error = bwn_fw_get(mac, type, filename, &fw->initvals_band); 4044 if (error) { 4045 bwn_release_firmware(mac); 4046 return (error); 4047 } 4048 return (0); 4049fail1: 4050 device_printf(sc->sc_dev, "no INITVALS for rev %d, phy.type %d\n", 4051 rev, mac->mac_phy.type); 4052 bwn_release_firmware(mac); 4053 return (EOPNOTSUPP); 4054} 4055 4056static int 4057bwn_fw_get(struct bwn_mac *mac, enum bwn_fwtype type, 4058 const char *name, struct bwn_fwfile *bfw) 4059{ 4060 const struct bwn_fwhdr *hdr; 4061 struct bwn_softc *sc = mac->mac_sc; 4062 const struct firmware *fw; 4063 char namebuf[64]; 4064 4065 if (name == NULL) { 4066 bwn_do_release_fw(bfw); 4067 return (0); 4068 } 4069 if (bfw->filename != NULL) { 4070 if (bfw->type == type && (strcmp(bfw->filename, name) == 0)) 4071 return (0); 4072 bwn_do_release_fw(bfw); 4073 } 4074 4075 snprintf(namebuf, sizeof(namebuf), "bwn%s_v4_%s%s", 4076 (type == BWN_FWTYPE_OPENSOURCE) ? "-open" : "", 4077 (mac->mac_phy.type == BWN_PHYTYPE_LP) ? "lp_" : "", name); 4078 /* XXX Sleeping on "fwload" with the non-sleepable locks held */ 4079 fw = firmware_get(namebuf); 4080 if (fw == NULL) { 4081 device_printf(sc->sc_dev, "the fw file(%s) not found\n", 4082 namebuf); 4083 return (ENOENT); 4084 } 4085 if (fw->datasize < sizeof(struct bwn_fwhdr)) 4086 goto fail; 4087 hdr = (const struct bwn_fwhdr *)(fw->data); 4088 switch (hdr->type) { 4089 case BWN_FWTYPE_UCODE: 4090 case BWN_FWTYPE_PCM: 4091 if (be32toh(hdr->size) != 4092 (fw->datasize - sizeof(struct bwn_fwhdr))) 4093 goto fail; 4094 /* FALLTHROUGH */ 4095 case BWN_FWTYPE_IV: 4096 if (hdr->ver != 1) 4097 goto fail; 4098 break; 4099 default: 4100 goto fail; 4101 } 4102 bfw->filename = name; 4103 bfw->fw = fw; 4104 bfw->type = type; 4105 return (0); 4106fail: 4107 device_printf(sc->sc_dev, "the fw file(%s) format error\n", namebuf); 4108 if (fw != NULL) 4109 firmware_put(fw, FIRMWARE_UNLOAD); 4110 return (EPROTO); 4111} 4112 4113static void 4114bwn_release_firmware(struct bwn_mac *mac) 4115{ 4116 4117 bwn_do_release_fw(&mac->mac_fw.ucode); 4118 bwn_do_release_fw(&mac->mac_fw.pcm); 4119 bwn_do_release_fw(&mac->mac_fw.initvals); 4120 bwn_do_release_fw(&mac->mac_fw.initvals_band); 4121} 4122 4123static void 4124bwn_do_release_fw(struct bwn_fwfile *bfw) 4125{ 4126 4127 if (bfw->fw != NULL) 4128 firmware_put(bfw->fw, FIRMWARE_UNLOAD); 4129 bfw->fw = NULL; 4130 bfw->filename = NULL; 4131} 4132 4133static int 4134bwn_fw_loaducode(struct bwn_mac *mac) 4135{ 4136#define GETFWOFFSET(fwp, offset) \ 4137 ((const uint32_t *)((const char *)fwp.fw->data + offset)) 4138#define GETFWSIZE(fwp, offset) \ 4139 ((fwp.fw->datasize - offset) / sizeof(uint32_t)) 4140 struct bwn_softc *sc = mac->mac_sc; 4141 const uint32_t *data; 4142 unsigned int i; 4143 uint32_t ctl; 4144 uint16_t date, fwcaps, time; 4145 int error = 0; 4146 4147 ctl = BWN_READ_4(mac, BWN_MACCTL); 4148 ctl |= BWN_MACCTL_MCODE_JMP0; 4149 KASSERT(!(ctl & BWN_MACCTL_MCODE_RUN), ("%s:%d: fail", __func__, 4150 __LINE__)); 4151 BWN_WRITE_4(mac, BWN_MACCTL, ctl); 4152 for (i = 0; i < 64; i++) 4153 bwn_shm_write_2(mac, BWN_SCRATCH, i, 0); 4154 for (i = 0; i < 4096; i += 2) 4155 bwn_shm_write_2(mac, BWN_SHARED, i, 0); 4156 4157 data = GETFWOFFSET(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr)); 4158 bwn_shm_ctlword(mac, BWN_UCODE | BWN_SHARED_AUTOINC, 0x0000); 4159 for (i = 0; i < GETFWSIZE(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr)); 4160 i++) { 4161 BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i])); 4162 DELAY(10); 4163 } 4164 4165 if (mac->mac_fw.pcm.fw) { 4166 data = GETFWOFFSET(mac->mac_fw.pcm, sizeof(struct bwn_fwhdr)); 4167 bwn_shm_ctlword(mac, BWN_HW, 0x01ea); 4168 BWN_WRITE_4(mac, BWN_SHM_DATA, 0x00004000); 4169 bwn_shm_ctlword(mac, BWN_HW, 0x01eb); 4170 for (i = 0; i < GETFWSIZE(mac->mac_fw.pcm, 4171 sizeof(struct bwn_fwhdr)); i++) { 4172 BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i])); 4173 DELAY(10); 4174 } 4175 } 4176 4177 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_ALL); 4178 BWN_WRITE_4(mac, BWN_MACCTL, 4179 (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_JMP0) | 4180 BWN_MACCTL_MCODE_RUN); 4181 4182 for (i = 0; i < 21; i++) { 4183 if (BWN_READ_4(mac, BWN_INTR_REASON) == BWN_INTR_MAC_SUSPENDED) 4184 break; 4185 if (i >= 20) { 4186 device_printf(sc->sc_dev, "ucode timeout\n"); 4187 error = ENXIO; 4188 goto error; 4189 } 4190 DELAY(50000); 4191 } 4192 BWN_READ_4(mac, BWN_INTR_REASON); 4193 4194 mac->mac_fw.rev = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_REV); 4195 if (mac->mac_fw.rev <= 0x128) { 4196 device_printf(sc->sc_dev, "the firmware is too old\n"); 4197 error = EOPNOTSUPP; 4198 goto error; 4199 } 4200 4201 /* 4202 * Determine firmware header version; needed for TX/RX packet 4203 * handling. 4204 */ 4205 if (mac->mac_fw.rev >= 598) 4206 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_598; 4207 else if (mac->mac_fw.rev >= 410) 4208 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_410; 4209 else 4210 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_351; 4211 4212 /* 4213 * We don't support rev 598 or later; that requires 4214 * another round of changes to the TX/RX descriptor 4215 * and status layout. 4216 * 4217 * So, complain this is the case and exit out, rather 4218 * than attaching and then failing. 4219 */ 4220#if 0 4221 if (mac->mac_fw.fw_hdr_format == BWN_FW_HDR_598) { 4222 device_printf(sc->sc_dev, 4223 "firmware is too new (>=598); not supported\n"); 4224 error = EOPNOTSUPP; 4225 goto error; 4226 } 4227#endif 4228 4229 mac->mac_fw.patch = bwn_shm_read_2(mac, BWN_SHARED, 4230 BWN_SHARED_UCODE_PATCH); 4231 date = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_DATE); 4232 mac->mac_fw.opensource = (date == 0xffff); 4233 if (bwn_wme != 0) 4234 mac->mac_flags |= BWN_MAC_FLAG_WME; 4235 mac->mac_flags |= BWN_MAC_FLAG_HWCRYPTO; 4236 4237 time = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_TIME); 4238 if (mac->mac_fw.opensource == 0) { 4239 device_printf(sc->sc_dev, 4240 "firmware version (rev %u patch %u date %#x time %#x)\n", 4241 mac->mac_fw.rev, mac->mac_fw.patch, date, time); 4242 if (mac->mac_fw.no_pcmfile) 4243 device_printf(sc->sc_dev, 4244 "no HW crypto acceleration due to pcm5\n"); 4245 } else { 4246 mac->mac_fw.patch = time; 4247 fwcaps = bwn_fwcaps_read(mac); 4248 if (!(fwcaps & BWN_FWCAPS_HWCRYPTO) || mac->mac_fw.no_pcmfile) { 4249 device_printf(sc->sc_dev, 4250 "disabling HW crypto acceleration\n"); 4251 mac->mac_flags &= ~BWN_MAC_FLAG_HWCRYPTO; 4252 } 4253 if (!(fwcaps & BWN_FWCAPS_WME)) { 4254 device_printf(sc->sc_dev, "disabling WME support\n"); 4255 mac->mac_flags &= ~BWN_MAC_FLAG_WME; 4256 } 4257 } 4258 4259 if (BWN_ISOLDFMT(mac)) 4260 device_printf(sc->sc_dev, "using old firmware image\n"); 4261 4262 return (0); 4263 4264error: 4265 BWN_WRITE_4(mac, BWN_MACCTL, 4266 (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_RUN) | 4267 BWN_MACCTL_MCODE_JMP0); 4268 4269 return (error); 4270#undef GETFWSIZE 4271#undef GETFWOFFSET 4272} 4273 4274/* OpenFirmware only */ 4275static uint16_t 4276bwn_fwcaps_read(struct bwn_mac *mac) 4277{ 4278 4279 KASSERT(mac->mac_fw.opensource == 1, 4280 ("%s:%d: fail", __func__, __LINE__)); 4281 return (bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_FWCAPS)); 4282} 4283 4284static int 4285bwn_fwinitvals_write(struct bwn_mac *mac, const struct bwn_fwinitvals *ivals, 4286 size_t count, size_t array_size) 4287{ 4288#define GET_NEXTIV16(iv) \ 4289 ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \ 4290 sizeof(uint16_t) + sizeof(uint16_t))) 4291#define GET_NEXTIV32(iv) \ 4292 ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \ 4293 sizeof(uint16_t) + sizeof(uint32_t))) 4294 struct bwn_softc *sc = mac->mac_sc; 4295 const struct bwn_fwinitvals *iv; 4296 uint16_t offset; 4297 size_t i; 4298 uint8_t bit32; 4299 4300 KASSERT(sizeof(struct bwn_fwinitvals) == 6, 4301 ("%s:%d: fail", __func__, __LINE__)); 4302 iv = ivals; 4303 for (i = 0; i < count; i++) { 4304 if (array_size < sizeof(iv->offset_size)) 4305 goto fail; 4306 array_size -= sizeof(iv->offset_size); 4307 offset = be16toh(iv->offset_size); 4308 bit32 = (offset & BWN_FWINITVALS_32BIT) ? 1 : 0; 4309 offset &= BWN_FWINITVALS_OFFSET_MASK; 4310 if (offset >= 0x1000) 4311 goto fail; 4312 if (bit32) { 4313 if (array_size < sizeof(iv->data.d32)) 4314 goto fail; 4315 array_size -= sizeof(iv->data.d32); 4316 BWN_WRITE_4(mac, offset, be32toh(iv->data.d32)); 4317 iv = GET_NEXTIV32(iv); 4318 } else { 4319 4320 if (array_size < sizeof(iv->data.d16)) 4321 goto fail; 4322 array_size -= sizeof(iv->data.d16); 4323 BWN_WRITE_2(mac, offset, be16toh(iv->data.d16)); 4324 4325 iv = GET_NEXTIV16(iv); 4326 } 4327 } 4328 if (array_size != 0) 4329 goto fail; 4330 return (0); 4331fail: 4332 device_printf(sc->sc_dev, "initvals: invalid format\n"); 4333 return (EPROTO); 4334#undef GET_NEXTIV16 4335#undef GET_NEXTIV32 4336} 4337 4338int 4339bwn_switch_channel(struct bwn_mac *mac, int chan) 4340{ 4341 struct bwn_phy *phy = &(mac->mac_phy); 4342 struct bwn_softc *sc = mac->mac_sc; 4343 struct ieee80211com *ic = &sc->sc_ic; 4344 uint16_t channelcookie, savedcookie; 4345 int error; 4346 4347 if (chan == 0xffff) 4348 chan = phy->get_default_chan(mac); 4349 4350 channelcookie = chan; 4351 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 4352 channelcookie |= 0x100; 4353 savedcookie = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_CHAN); 4354 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, channelcookie); 4355 error = phy->switch_channel(mac, chan); 4356 if (error) 4357 goto fail; 4358 4359 mac->mac_phy.chan = chan; 4360 DELAY(8000); 4361 return (0); 4362fail: 4363 device_printf(sc->sc_dev, "failed to switch channel\n"); 4364 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, savedcookie); 4365 return (error); 4366} 4367 4368static uint16_t 4369bwn_ant2phy(int antenna) 4370{ 4371 4372 switch (antenna) { 4373 case BWN_ANT0: 4374 return (BWN_TX_PHY_ANT0); 4375 case BWN_ANT1: 4376 return (BWN_TX_PHY_ANT1); 4377 case BWN_ANT2: 4378 return (BWN_TX_PHY_ANT2); 4379 case BWN_ANT3: 4380 return (BWN_TX_PHY_ANT3); 4381 case BWN_ANTAUTO: 4382 return (BWN_TX_PHY_ANT01AUTO); 4383 } 4384 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 4385 return (0); 4386} 4387 4388static void 4389bwn_wme_load(struct bwn_mac *mac) 4390{ 4391 struct bwn_softc *sc = mac->mac_sc; 4392 int i; 4393 4394 KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams), 4395 ("%s:%d: fail", __func__, __LINE__)); 4396 4397 bwn_mac_suspend(mac); 4398 for (i = 0; i < N(sc->sc_wmeParams); i++) 4399 bwn_wme_loadparams(mac, &(sc->sc_wmeParams[i]), 4400 bwn_wme_shm_offsets[i]); 4401 bwn_mac_enable(mac); 4402} 4403 4404static void 4405bwn_wme_loadparams(struct bwn_mac *mac, 4406 const struct wmeParams *p, uint16_t shm_offset) 4407{ 4408#define SM(_v, _f) (((_v) << _f##_S) & _f) 4409 struct bwn_softc *sc = mac->mac_sc; 4410 uint16_t params[BWN_NR_WMEPARAMS]; 4411 int slot, tmp; 4412 unsigned int i; 4413 4414 slot = BWN_READ_2(mac, BWN_RNG) & 4415 SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN); 4416 4417 memset(¶ms, 0, sizeof(params)); 4418 4419 DPRINTF(sc, BWN_DEBUG_WME, "wmep_txopLimit %d wmep_logcwmin %d " 4420 "wmep_logcwmax %d wmep_aifsn %d\n", p->wmep_txopLimit, 4421 p->wmep_logcwmin, p->wmep_logcwmax, p->wmep_aifsn); 4422 4423 params[BWN_WMEPARAM_TXOP] = p->wmep_txopLimit * 32; 4424 params[BWN_WMEPARAM_CWMIN] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN); 4425 params[BWN_WMEPARAM_CWMAX] = SM(p->wmep_logcwmax, WME_PARAM_LOGCWMAX); 4426 params[BWN_WMEPARAM_CWCUR] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN); 4427 params[BWN_WMEPARAM_AIFS] = p->wmep_aifsn; 4428 params[BWN_WMEPARAM_BSLOTS] = slot; 4429 params[BWN_WMEPARAM_REGGAP] = slot + p->wmep_aifsn; 4430 4431 for (i = 0; i < N(params); i++) { 4432 if (i == BWN_WMEPARAM_STATUS) { 4433 tmp = bwn_shm_read_2(mac, BWN_SHARED, 4434 shm_offset + (i * 2)); 4435 tmp |= 0x100; 4436 bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2), 4437 tmp); 4438 } else { 4439 bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2), 4440 params[i]); 4441 } 4442 } 4443} 4444 4445static void 4446bwn_mac_write_bssid(struct bwn_mac *mac) 4447{ 4448 struct bwn_softc *sc = mac->mac_sc; 4449 uint32_t tmp; 4450 int i; 4451 uint8_t mac_bssid[IEEE80211_ADDR_LEN * 2]; 4452 4453 bwn_mac_setfilter(mac, BWN_MACFILTER_BSSID, sc->sc_bssid); 4454 memcpy(mac_bssid, sc->sc_ic.ic_macaddr, IEEE80211_ADDR_LEN); 4455 memcpy(mac_bssid + IEEE80211_ADDR_LEN, sc->sc_bssid, 4456 IEEE80211_ADDR_LEN); 4457 4458 for (i = 0; i < N(mac_bssid); i += sizeof(uint32_t)) { 4459 tmp = (uint32_t) (mac_bssid[i + 0]); 4460 tmp |= (uint32_t) (mac_bssid[i + 1]) << 8; 4461 tmp |= (uint32_t) (mac_bssid[i + 2]) << 16; 4462 tmp |= (uint32_t) (mac_bssid[i + 3]) << 24; 4463 bwn_ram_write(mac, 0x20 + i, tmp); 4464 } 4465} 4466 4467static void 4468bwn_mac_setfilter(struct bwn_mac *mac, uint16_t offset, 4469 const uint8_t *macaddr) 4470{ 4471 static const uint8_t zero[IEEE80211_ADDR_LEN] = { 0 }; 4472 uint16_t data; 4473 4474 if (!mac) 4475 macaddr = zero; 4476 4477 offset |= 0x0020; 4478 BWN_WRITE_2(mac, BWN_MACFILTER_CONTROL, offset); 4479 4480 data = macaddr[0]; 4481 data |= macaddr[1] << 8; 4482 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data); 4483 data = macaddr[2]; 4484 data |= macaddr[3] << 8; 4485 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data); 4486 data = macaddr[4]; 4487 data |= macaddr[5] << 8; 4488 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data); 4489} 4490 4491static void 4492bwn_key_dowrite(struct bwn_mac *mac, uint8_t index, uint8_t algorithm, 4493 const uint8_t *key, size_t key_len, const uint8_t *mac_addr) 4494{ 4495 uint8_t buf[BWN_SEC_KEYSIZE] = { 0, }; 4496 uint8_t per_sta_keys_start = 8; 4497 4498 if (BWN_SEC_NEWAPI(mac)) 4499 per_sta_keys_start = 4; 4500 4501 KASSERT(index < mac->mac_max_nr_keys, 4502 ("%s:%d: fail", __func__, __LINE__)); 4503 KASSERT(key_len <= BWN_SEC_KEYSIZE, 4504 ("%s:%d: fail", __func__, __LINE__)); 4505 4506 if (index >= per_sta_keys_start) 4507 bwn_key_macwrite(mac, index, NULL); 4508 if (key) 4509 memcpy(buf, key, key_len); 4510 bwn_key_write(mac, index, algorithm, buf); 4511 if (index >= per_sta_keys_start) 4512 bwn_key_macwrite(mac, index, mac_addr); 4513 4514 mac->mac_key[index].algorithm = algorithm; 4515} 4516 4517static void 4518bwn_key_macwrite(struct bwn_mac *mac, uint8_t index, const uint8_t *addr) 4519{ 4520 struct bwn_softc *sc = mac->mac_sc; 4521 uint32_t addrtmp[2] = { 0, 0 }; 4522 uint8_t start = 8; 4523 4524 if (BWN_SEC_NEWAPI(mac)) 4525 start = 4; 4526 4527 KASSERT(index >= start, 4528 ("%s:%d: fail", __func__, __LINE__)); 4529 index -= start; 4530 4531 if (addr) { 4532 addrtmp[0] = addr[0]; 4533 addrtmp[0] |= ((uint32_t) (addr[1]) << 8); 4534 addrtmp[0] |= ((uint32_t) (addr[2]) << 16); 4535 addrtmp[0] |= ((uint32_t) (addr[3]) << 24); 4536 addrtmp[1] = addr[4]; 4537 addrtmp[1] |= ((uint32_t) (addr[5]) << 8); 4538 } 4539 4540 if (siba_get_revid(sc->sc_dev) >= 5) { 4541 bwn_shm_write_4(mac, BWN_RCMTA, (index * 2) + 0, addrtmp[0]); 4542 bwn_shm_write_2(mac, BWN_RCMTA, (index * 2) + 1, addrtmp[1]); 4543 } else { 4544 if (index >= 8) { 4545 bwn_shm_write_4(mac, BWN_SHARED, 4546 BWN_SHARED_PSM + (index * 6) + 0, addrtmp[0]); 4547 bwn_shm_write_2(mac, BWN_SHARED, 4548 BWN_SHARED_PSM + (index * 6) + 4, addrtmp[1]); 4549 } 4550 } 4551} 4552 4553static void 4554bwn_key_write(struct bwn_mac *mac, uint8_t index, uint8_t algorithm, 4555 const uint8_t *key) 4556{ 4557 unsigned int i; 4558 uint32_t offset; 4559 uint16_t kidx, value; 4560 4561 kidx = BWN_SEC_KEY2FW(mac, index); 4562 bwn_shm_write_2(mac, BWN_SHARED, 4563 BWN_SHARED_KEYIDX_BLOCK + (kidx * 2), (kidx << 4) | algorithm); 4564 4565 offset = mac->mac_ktp + (index * BWN_SEC_KEYSIZE); 4566 for (i = 0; i < BWN_SEC_KEYSIZE; i += 2) { 4567 value = key[i]; 4568 value |= (uint16_t)(key[i + 1]) << 8; 4569 bwn_shm_write_2(mac, BWN_SHARED, offset + i, value); 4570 } 4571} 4572 4573static void 4574bwn_phy_exit(struct bwn_mac *mac) 4575{ 4576 4577 mac->mac_phy.rf_onoff(mac, 0); 4578 if (mac->mac_phy.exit != NULL) 4579 mac->mac_phy.exit(mac); 4580} 4581 4582static void 4583bwn_dma_free(struct bwn_mac *mac) 4584{ 4585 struct bwn_dma *dma; 4586 4587 if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0) 4588 return; 4589 dma = &mac->mac_method.dma; 4590 4591 bwn_dma_ringfree(&dma->rx); 4592 bwn_dma_ringfree(&dma->wme[WME_AC_BK]); 4593 bwn_dma_ringfree(&dma->wme[WME_AC_BE]); 4594 bwn_dma_ringfree(&dma->wme[WME_AC_VI]); 4595 bwn_dma_ringfree(&dma->wme[WME_AC_VO]); 4596 bwn_dma_ringfree(&dma->mcast); 4597} 4598 4599static void 4600bwn_core_stop(struct bwn_mac *mac) 4601{ 4602 struct bwn_softc *sc = mac->mac_sc; 4603 4604 BWN_ASSERT_LOCKED(sc); 4605 4606 if (mac->mac_status < BWN_MAC_STATUS_STARTED) 4607 return; 4608 4609 callout_stop(&sc->sc_rfswitch_ch); 4610 callout_stop(&sc->sc_task_ch); 4611 callout_stop(&sc->sc_watchdog_ch); 4612 sc->sc_watchdog_timer = 0; 4613 BWN_WRITE_4(mac, BWN_INTR_MASK, 0); 4614 BWN_READ_4(mac, BWN_INTR_MASK); 4615 bwn_mac_suspend(mac); 4616 4617 mac->mac_status = BWN_MAC_STATUS_INITED; 4618} 4619 4620static int 4621bwn_switch_band(struct bwn_softc *sc, struct ieee80211_channel *chan) 4622{ 4623 struct bwn_mac *up_dev = NULL; 4624 struct bwn_mac *down_dev; 4625 struct bwn_mac *mac; 4626 int err, status; 4627 uint8_t gmode; 4628 4629 BWN_ASSERT_LOCKED(sc); 4630 4631 TAILQ_FOREACH(mac, &sc->sc_maclist, mac_list) { 4632 if (IEEE80211_IS_CHAN_2GHZ(chan) && 4633 mac->mac_phy.supports_2ghz) { 4634 up_dev = mac; 4635 gmode = 1; 4636 } else if (IEEE80211_IS_CHAN_5GHZ(chan) && 4637 mac->mac_phy.supports_5ghz) { 4638 up_dev = mac; 4639 gmode = 0; 4640 } else { 4641 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 4642 return (EINVAL); 4643 } 4644 if (up_dev != NULL) 4645 break; 4646 } 4647 if (up_dev == NULL) { 4648 device_printf(sc->sc_dev, "Could not find a device\n"); 4649 return (ENODEV); 4650 } 4651 if (up_dev == sc->sc_curmac && sc->sc_curmac->mac_phy.gmode == gmode) 4652 return (0); 4653 4654 DPRINTF(sc, BWN_DEBUG_RF | BWN_DEBUG_PHY | BWN_DEBUG_RESET, 4655 "switching to %s-GHz band\n", 4656 IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5"); 4657 4658 down_dev = sc->sc_curmac; 4659 status = down_dev->mac_status; 4660 if (status >= BWN_MAC_STATUS_STARTED) 4661 bwn_core_stop(down_dev); 4662 if (status >= BWN_MAC_STATUS_INITED) 4663 bwn_core_exit(down_dev); 4664 4665 if (down_dev != up_dev) 4666 bwn_phy_reset(down_dev); 4667 4668 up_dev->mac_phy.gmode = gmode; 4669 if (status >= BWN_MAC_STATUS_INITED) { 4670 err = bwn_core_init(up_dev); 4671 if (err) { 4672 device_printf(sc->sc_dev, 4673 "fatal: failed to initialize for %s-GHz\n", 4674 IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5"); 4675 goto fail; 4676 } 4677 } 4678 if (status >= BWN_MAC_STATUS_STARTED) 4679 bwn_core_start(up_dev); 4680 KASSERT(up_dev->mac_status == status, ("%s: fail", __func__)); 4681 sc->sc_curmac = up_dev; 4682 4683 return (0); 4684fail: 4685 sc->sc_curmac = NULL; 4686 return (err); 4687} 4688 4689static void 4690bwn_rf_turnon(struct bwn_mac *mac) 4691{ 4692 4693 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__); 4694 4695 bwn_mac_suspend(mac); 4696 mac->mac_phy.rf_onoff(mac, 1); 4697 mac->mac_phy.rf_on = 1; 4698 bwn_mac_enable(mac); 4699} 4700 4701static void 4702bwn_rf_turnoff(struct bwn_mac *mac) 4703{ 4704 4705 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__); 4706 4707 bwn_mac_suspend(mac); 4708 mac->mac_phy.rf_onoff(mac, 0); 4709 mac->mac_phy.rf_on = 0; 4710 bwn_mac_enable(mac); 4711} 4712 4713/* 4714 * SSB PHY reset. 4715 */ 4716static void 4717bwn_phy_reset_siba(struct bwn_mac *mac) 4718{ 4719 struct bwn_softc *sc = mac->mac_sc; 4720 4721 siba_write_4(sc->sc_dev, SIBA_TGSLOW, 4722 ((siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~BWN_TGSLOW_SUPPORT_G) | 4723 BWN_TGSLOW_PHYRESET) | SIBA_TGSLOW_FGC); 4724 DELAY(1000); 4725 siba_write_4(sc->sc_dev, SIBA_TGSLOW, 4726 (siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~SIBA_TGSLOW_FGC)); 4727 DELAY(1000); 4728} 4729 4730static void 4731bwn_phy_reset(struct bwn_mac *mac) 4732{ 4733 4734 if (bwn_is_bus_siba(mac)) { 4735 bwn_phy_reset_siba(mac); 4736 } else { 4737 BWN_ERRPRINTF(mac->mac_sc, "%s: unknown bus!\n", __func__); 4738 } 4739} 4740 4741static int 4742bwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 4743{ 4744 struct bwn_vap *bvp = BWN_VAP(vap); 4745 struct ieee80211com *ic= vap->iv_ic; 4746 enum ieee80211_state ostate = vap->iv_state; 4747 struct bwn_softc *sc = ic->ic_softc; 4748 struct bwn_mac *mac = sc->sc_curmac; 4749 int error; 4750 4751 DPRINTF(sc, BWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4752 ieee80211_state_name[vap->iv_state], 4753 ieee80211_state_name[nstate]); 4754 4755 error = bvp->bv_newstate(vap, nstate, arg); 4756 if (error != 0) 4757 return (error); 4758 4759 BWN_LOCK(sc); 4760 4761 bwn_led_newstate(mac, nstate); 4762 4763 /* 4764 * Clear the BSSID when we stop a STA 4765 */ 4766 if (vap->iv_opmode == IEEE80211_M_STA) { 4767 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 4768 /* 4769 * Clear out the BSSID. If we reassociate to 4770 * the same AP, this will reinialize things 4771 * correctly... 4772 */ 4773 if (ic->ic_opmode == IEEE80211_M_STA && 4774 (sc->sc_flags & BWN_FLAG_INVALID) == 0) { 4775 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 4776 bwn_set_macaddr(mac); 4777 } 4778 } 4779 } 4780 4781 if (vap->iv_opmode == IEEE80211_M_MONITOR || 4782 vap->iv_opmode == IEEE80211_M_AHDEMO) { 4783 /* XXX nothing to do? */ 4784 } else if (nstate == IEEE80211_S_RUN) { 4785 memcpy(sc->sc_bssid, vap->iv_bss->ni_bssid, IEEE80211_ADDR_LEN); 4786 bwn_set_opmode(mac); 4787 bwn_set_pretbtt(mac); 4788 bwn_spu_setdelay(mac, 0); 4789 bwn_set_macaddr(mac); 4790 } 4791 4792 BWN_UNLOCK(sc); 4793 4794 return (error); 4795} 4796 4797static void 4798bwn_set_pretbtt(struct bwn_mac *mac) 4799{ 4800 struct bwn_softc *sc = mac->mac_sc; 4801 struct ieee80211com *ic = &sc->sc_ic; 4802 uint16_t pretbtt; 4803 4804 if (ic->ic_opmode == IEEE80211_M_IBSS) 4805 pretbtt = 2; 4806 else 4807 pretbtt = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 120 : 250; 4808 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PRETBTT, pretbtt); 4809 BWN_WRITE_2(mac, BWN_TSF_CFP_PRETBTT, pretbtt); 4810} 4811 4812static int 4813bwn_intr(void *arg) 4814{ 4815 struct bwn_mac *mac = arg; 4816 struct bwn_softc *sc = mac->mac_sc; 4817 uint32_t reason; 4818 4819 if (mac->mac_status < BWN_MAC_STATUS_STARTED || 4820 (sc->sc_flags & BWN_FLAG_INVALID)) 4821 return (FILTER_STRAY); 4822 4823 DPRINTF(sc, BWN_DEBUG_INTR, "%s: called\n", __func__); 4824 4825 reason = BWN_READ_4(mac, BWN_INTR_REASON); 4826 if (reason == 0xffffffff) /* shared IRQ */ 4827 return (FILTER_STRAY); 4828 reason &= mac->mac_intr_mask; 4829 if (reason == 0) 4830 return (FILTER_HANDLED); 4831 DPRINTF(sc, BWN_DEBUG_INTR, "%s: reason=0x%08x\n", __func__, reason); 4832 4833 mac->mac_reason[0] = BWN_READ_4(mac, BWN_DMA0_REASON) & 0x0001dc00; 4834 mac->mac_reason[1] = BWN_READ_4(mac, BWN_DMA1_REASON) & 0x0000dc00; 4835 mac->mac_reason[2] = BWN_READ_4(mac, BWN_DMA2_REASON) & 0x0000dc00; 4836 mac->mac_reason[3] = BWN_READ_4(mac, BWN_DMA3_REASON) & 0x0001dc00; 4837 mac->mac_reason[4] = BWN_READ_4(mac, BWN_DMA4_REASON) & 0x0000dc00; 4838 BWN_WRITE_4(mac, BWN_INTR_REASON, reason); 4839 BWN_WRITE_4(mac, BWN_DMA0_REASON, mac->mac_reason[0]); 4840 BWN_WRITE_4(mac, BWN_DMA1_REASON, mac->mac_reason[1]); 4841 BWN_WRITE_4(mac, BWN_DMA2_REASON, mac->mac_reason[2]); 4842 BWN_WRITE_4(mac, BWN_DMA3_REASON, mac->mac_reason[3]); 4843 BWN_WRITE_4(mac, BWN_DMA4_REASON, mac->mac_reason[4]); 4844 4845 /* Disable interrupts. */ 4846 BWN_WRITE_4(mac, BWN_INTR_MASK, 0); 4847 4848 mac->mac_reason_intr = reason; 4849 4850 BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ); 4851 BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE); 4852 4853 taskqueue_enqueue(sc->sc_tq, &mac->mac_intrtask); 4854 return (FILTER_HANDLED); 4855} 4856 4857static void 4858bwn_intrtask(void *arg, int npending) 4859{ 4860 struct bwn_mac *mac = arg; 4861 struct bwn_softc *sc = mac->mac_sc; 4862 uint32_t merged = 0; 4863 int i, tx = 0, rx = 0; 4864 4865 BWN_LOCK(sc); 4866 if (mac->mac_status < BWN_MAC_STATUS_STARTED || 4867 (sc->sc_flags & BWN_FLAG_INVALID)) { 4868 BWN_UNLOCK(sc); 4869 return; 4870 } 4871 4872 for (i = 0; i < N(mac->mac_reason); i++) 4873 merged |= mac->mac_reason[i]; 4874 4875 if (mac->mac_reason_intr & BWN_INTR_MAC_TXERR) 4876 device_printf(sc->sc_dev, "MAC trans error\n"); 4877 4878 if (mac->mac_reason_intr & BWN_INTR_PHY_TXERR) { 4879 DPRINTF(sc, BWN_DEBUG_INTR, "%s: PHY trans error\n", __func__); 4880 mac->mac_phy.txerrors--; 4881 if (mac->mac_phy.txerrors == 0) { 4882 mac->mac_phy.txerrors = BWN_TXERROR_MAX; 4883 bwn_restart(mac, "PHY TX errors"); 4884 } 4885 } 4886 4887 if (merged & (BWN_DMAINTR_FATALMASK | BWN_DMAINTR_NONFATALMASK)) { 4888 if (merged & BWN_DMAINTR_FATALMASK) { 4889 device_printf(sc->sc_dev, 4890 "Fatal DMA error: %#x %#x %#x %#x %#x %#x\n", 4891 mac->mac_reason[0], mac->mac_reason[1], 4892 mac->mac_reason[2], mac->mac_reason[3], 4893 mac->mac_reason[4], mac->mac_reason[5]); 4894 bwn_restart(mac, "DMA error"); 4895 BWN_UNLOCK(sc); 4896 return; 4897 } 4898 if (merged & BWN_DMAINTR_NONFATALMASK) { 4899 device_printf(sc->sc_dev, 4900 "DMA error: %#x %#x %#x %#x %#x %#x\n", 4901 mac->mac_reason[0], mac->mac_reason[1], 4902 mac->mac_reason[2], mac->mac_reason[3], 4903 mac->mac_reason[4], mac->mac_reason[5]); 4904 } 4905 } 4906 4907 if (mac->mac_reason_intr & BWN_INTR_UCODE_DEBUG) 4908 bwn_intr_ucode_debug(mac); 4909 if (mac->mac_reason_intr & BWN_INTR_TBTT_INDI) 4910 bwn_intr_tbtt_indication(mac); 4911 if (mac->mac_reason_intr & BWN_INTR_ATIM_END) 4912 bwn_intr_atim_end(mac); 4913 if (mac->mac_reason_intr & BWN_INTR_BEACON) 4914 bwn_intr_beacon(mac); 4915 if (mac->mac_reason_intr & BWN_INTR_PMQ) 4916 bwn_intr_pmq(mac); 4917 if (mac->mac_reason_intr & BWN_INTR_NOISESAMPLE_OK) 4918 bwn_intr_noise(mac); 4919 4920 if (mac->mac_flags & BWN_MAC_FLAG_DMA) { 4921 if (mac->mac_reason[0] & BWN_DMAINTR_RX_DONE) { 4922 bwn_dma_rx(mac->mac_method.dma.rx); 4923 rx = 1; 4924 } 4925 } else 4926 rx = bwn_pio_rx(&mac->mac_method.pio.rx); 4927 4928 KASSERT(!(mac->mac_reason[1] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 4929 KASSERT(!(mac->mac_reason[2] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 4930 KASSERT(!(mac->mac_reason[3] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 4931 KASSERT(!(mac->mac_reason[4] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 4932 KASSERT(!(mac->mac_reason[5] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 4933 4934 if (mac->mac_reason_intr & BWN_INTR_TX_OK) { 4935 bwn_intr_txeof(mac); 4936 tx = 1; 4937 } 4938 4939 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask); 4940 4941 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 4942 int evt = BWN_LED_EVENT_NONE; 4943 4944 if (tx && rx) { 4945 if (sc->sc_rx_rate > sc->sc_tx_rate) 4946 evt = BWN_LED_EVENT_RX; 4947 else 4948 evt = BWN_LED_EVENT_TX; 4949 } else if (tx) { 4950 evt = BWN_LED_EVENT_TX; 4951 } else if (rx) { 4952 evt = BWN_LED_EVENT_RX; 4953 } else if (rx == 0) { 4954 evt = BWN_LED_EVENT_POLL; 4955 } 4956 4957 if (evt != BWN_LED_EVENT_NONE) 4958 bwn_led_event(mac, evt); 4959 } 4960 4961 if (mbufq_first(&sc->sc_snd) != NULL) 4962 bwn_start(sc); 4963 4964 BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ); 4965 BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE); 4966 4967 BWN_UNLOCK(sc); 4968} 4969 4970static void 4971bwn_restart(struct bwn_mac *mac, const char *msg) 4972{ 4973 struct bwn_softc *sc = mac->mac_sc; 4974 struct ieee80211com *ic = &sc->sc_ic; 4975 4976 if (mac->mac_status < BWN_MAC_STATUS_INITED) 4977 return; 4978 4979 device_printf(sc->sc_dev, "HW reset: %s\n", msg); 4980 ieee80211_runtask(ic, &mac->mac_hwreset); 4981} 4982 4983static void 4984bwn_intr_ucode_debug(struct bwn_mac *mac) 4985{ 4986 struct bwn_softc *sc = mac->mac_sc; 4987 uint16_t reason; 4988 4989 if (mac->mac_fw.opensource == 0) 4990 return; 4991 4992 reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG); 4993 switch (reason) { 4994 case BWN_DEBUGINTR_PANIC: 4995 bwn_handle_fwpanic(mac); 4996 break; 4997 case BWN_DEBUGINTR_DUMP_SHM: 4998 device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_SHM\n"); 4999 break; 5000 case BWN_DEBUGINTR_DUMP_REGS: 5001 device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_REGS\n"); 5002 break; 5003 case BWN_DEBUGINTR_MARKER: 5004 device_printf(sc->sc_dev, "BWN_DEBUGINTR_MARKER\n"); 5005 break; 5006 default: 5007 device_printf(sc->sc_dev, 5008 "ucode debug unknown reason: %#x\n", reason); 5009 } 5010 5011 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG, 5012 BWN_DEBUGINTR_ACK); 5013} 5014 5015static void 5016bwn_intr_tbtt_indication(struct bwn_mac *mac) 5017{ 5018 struct bwn_softc *sc = mac->mac_sc; 5019 struct ieee80211com *ic = &sc->sc_ic; 5020 5021 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 5022 bwn_psctl(mac, 0); 5023 if (ic->ic_opmode == IEEE80211_M_IBSS) 5024 mac->mac_flags |= BWN_MAC_FLAG_DFQVALID; 5025} 5026 5027static void 5028bwn_intr_atim_end(struct bwn_mac *mac) 5029{ 5030 5031 if (mac->mac_flags & BWN_MAC_FLAG_DFQVALID) { 5032 BWN_WRITE_4(mac, BWN_MACCMD, 5033 BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_DFQ_VALID); 5034 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID; 5035 } 5036} 5037 5038static void 5039bwn_intr_beacon(struct bwn_mac *mac) 5040{ 5041 struct bwn_softc *sc = mac->mac_sc; 5042 struct ieee80211com *ic = &sc->sc_ic; 5043 uint32_t cmd, beacon0, beacon1; 5044 5045 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 5046 ic->ic_opmode == IEEE80211_M_MBSS) 5047 return; 5048 5049 mac->mac_intr_mask &= ~BWN_INTR_BEACON; 5050 5051 cmd = BWN_READ_4(mac, BWN_MACCMD); 5052 beacon0 = (cmd & BWN_MACCMD_BEACON0_VALID); 5053 beacon1 = (cmd & BWN_MACCMD_BEACON1_VALID); 5054 5055 if (beacon0 && beacon1) { 5056 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_BEACON); 5057 mac->mac_intr_mask |= BWN_INTR_BEACON; 5058 return; 5059 } 5060 5061 if (sc->sc_flags & BWN_FLAG_NEED_BEACON_TP) { 5062 sc->sc_flags &= ~BWN_FLAG_NEED_BEACON_TP; 5063 bwn_load_beacon0(mac); 5064 bwn_load_beacon1(mac); 5065 cmd = BWN_READ_4(mac, BWN_MACCMD); 5066 cmd |= BWN_MACCMD_BEACON0_VALID; 5067 BWN_WRITE_4(mac, BWN_MACCMD, cmd); 5068 } else { 5069 if (!beacon0) { 5070 bwn_load_beacon0(mac); 5071 cmd = BWN_READ_4(mac, BWN_MACCMD); 5072 cmd |= BWN_MACCMD_BEACON0_VALID; 5073 BWN_WRITE_4(mac, BWN_MACCMD, cmd); 5074 } else if (!beacon1) { 5075 bwn_load_beacon1(mac); 5076 cmd = BWN_READ_4(mac, BWN_MACCMD); 5077 cmd |= BWN_MACCMD_BEACON1_VALID; 5078 BWN_WRITE_4(mac, BWN_MACCMD, cmd); 5079 } 5080 } 5081} 5082 5083static void 5084bwn_intr_pmq(struct bwn_mac *mac) 5085{ 5086 uint32_t tmp; 5087 5088 while (1) { 5089 tmp = BWN_READ_4(mac, BWN_PS_STATUS); 5090 if (!(tmp & 0x00000008)) 5091 break; 5092 } 5093 BWN_WRITE_2(mac, BWN_PS_STATUS, 0x0002); 5094} 5095 5096static void 5097bwn_intr_noise(struct bwn_mac *mac) 5098{ 5099 struct bwn_phy_g *pg = &mac->mac_phy.phy_g; 5100 uint16_t tmp; 5101 uint8_t noise[4]; 5102 uint8_t i, j; 5103 int32_t average; 5104 5105 if (mac->mac_phy.type != BWN_PHYTYPE_G) 5106 return; 5107 5108 KASSERT(mac->mac_noise.noi_running, ("%s: fail", __func__)); 5109 *((uint32_t *)noise) = htole32(bwn_jssi_read(mac)); 5110 if (noise[0] == 0x7f || noise[1] == 0x7f || noise[2] == 0x7f || 5111 noise[3] == 0x7f) 5112 goto new; 5113 5114 KASSERT(mac->mac_noise.noi_nsamples < 8, 5115 ("%s:%d: fail", __func__, __LINE__)); 5116 i = mac->mac_noise.noi_nsamples; 5117 noise[0] = MIN(MAX(noise[0], 0), N(pg->pg_nrssi_lt) - 1); 5118 noise[1] = MIN(MAX(noise[1], 0), N(pg->pg_nrssi_lt) - 1); 5119 noise[2] = MIN(MAX(noise[2], 0), N(pg->pg_nrssi_lt) - 1); 5120 noise[3] = MIN(MAX(noise[3], 0), N(pg->pg_nrssi_lt) - 1); 5121 mac->mac_noise.noi_samples[i][0] = pg->pg_nrssi_lt[noise[0]]; 5122 mac->mac_noise.noi_samples[i][1] = pg->pg_nrssi_lt[noise[1]]; 5123 mac->mac_noise.noi_samples[i][2] = pg->pg_nrssi_lt[noise[2]]; 5124 mac->mac_noise.noi_samples[i][3] = pg->pg_nrssi_lt[noise[3]]; 5125 mac->mac_noise.noi_nsamples++; 5126 if (mac->mac_noise.noi_nsamples == 8) { 5127 average = 0; 5128 for (i = 0; i < 8; i++) { 5129 for (j = 0; j < 4; j++) 5130 average += mac->mac_noise.noi_samples[i][j]; 5131 } 5132 average = (((average / 32) * 125) + 64) / 128; 5133 tmp = (bwn_shm_read_2(mac, BWN_SHARED, 0x40c) / 128) & 0x1f; 5134 if (tmp >= 8) 5135 average += 2; 5136 else 5137 average -= 25; 5138 average -= (tmp == 8) ? 72 : 48; 5139 5140 mac->mac_stats.link_noise = average; 5141 mac->mac_noise.noi_running = 0; 5142 return; 5143 } 5144new: 5145 bwn_noise_gensample(mac); 5146} 5147 5148static int 5149bwn_pio_rx(struct bwn_pio_rxqueue *prq) 5150{ 5151 struct bwn_mac *mac = prq->prq_mac; 5152 struct bwn_softc *sc = mac->mac_sc; 5153 unsigned int i; 5154 5155 BWN_ASSERT_LOCKED(sc); 5156 5157 if (mac->mac_status < BWN_MAC_STATUS_STARTED) 5158 return (0); 5159 5160 for (i = 0; i < 5000; i++) { 5161 if (bwn_pio_rxeof(prq) == 0) 5162 break; 5163 } 5164 if (i >= 5000) 5165 device_printf(sc->sc_dev, "too many RX frames in PIO mode\n"); 5166 return ((i > 0) ? 1 : 0); 5167} 5168 5169static void 5170bwn_dma_rx(struct bwn_dma_ring *dr) 5171{ 5172 int slot, curslot; 5173 5174 KASSERT(!dr->dr_tx, ("%s:%d: fail", __func__, __LINE__)); 5175 curslot = dr->get_curslot(dr); 5176 KASSERT(curslot >= 0 && curslot < dr->dr_numslots, 5177 ("%s:%d: fail", __func__, __LINE__)); 5178 5179 slot = dr->dr_curslot; 5180 for (; slot != curslot; slot = bwn_dma_nextslot(dr, slot)) 5181 bwn_dma_rxeof(dr, &slot); 5182 5183 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 5184 BUS_DMASYNC_PREWRITE); 5185 5186 dr->set_curslot(dr, slot); 5187 dr->dr_curslot = slot; 5188} 5189 5190static void 5191bwn_intr_txeof(struct bwn_mac *mac) 5192{ 5193 struct bwn_txstatus stat; 5194 uint32_t stat0, stat1; 5195 uint16_t tmp; 5196 5197 BWN_ASSERT_LOCKED(mac->mac_sc); 5198 5199 while (1) { 5200 stat0 = BWN_READ_4(mac, BWN_XMITSTAT_0); 5201 if (!(stat0 & 0x00000001)) 5202 break; 5203 stat1 = BWN_READ_4(mac, BWN_XMITSTAT_1); 5204 5205 DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT, 5206 "%s: stat0=0x%08x, stat1=0x%08x\n", 5207 __func__, 5208 stat0, 5209 stat1); 5210 5211 stat.cookie = (stat0 >> 16); 5212 stat.seq = (stat1 & 0x0000ffff); 5213 stat.phy_stat = ((stat1 & 0x00ff0000) >> 16); 5214 tmp = (stat0 & 0x0000ffff); 5215 stat.framecnt = ((tmp & 0xf000) >> 12); 5216 stat.rtscnt = ((tmp & 0x0f00) >> 8); 5217 stat.sreason = ((tmp & 0x001c) >> 2); 5218 stat.pm = (tmp & 0x0080) ? 1 : 0; 5219 stat.im = (tmp & 0x0040) ? 1 : 0; 5220 stat.ampdu = (tmp & 0x0020) ? 1 : 0; 5221 stat.ack = (tmp & 0x0002) ? 1 : 0; 5222 5223 DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT, 5224 "%s: cookie=%d, seq=%d, phystat=0x%02x, framecnt=%d, " 5225 "rtscnt=%d, sreason=%d, pm=%d, im=%d, ampdu=%d, ack=%d\n", 5226 __func__, 5227 stat.cookie, 5228 stat.seq, 5229 stat.phy_stat, 5230 stat.framecnt, 5231 stat.rtscnt, 5232 stat.sreason, 5233 stat.pm, 5234 stat.im, 5235 stat.ampdu, 5236 stat.ack); 5237 5238 bwn_handle_txeof(mac, &stat); 5239 } 5240} 5241 5242static void 5243bwn_hwreset(void *arg, int npending) 5244{ 5245 struct bwn_mac *mac = arg; 5246 struct bwn_softc *sc = mac->mac_sc; 5247 int error = 0; 5248 int prev_status; 5249 5250 BWN_LOCK(sc); 5251 5252 prev_status = mac->mac_status; 5253 if (prev_status >= BWN_MAC_STATUS_STARTED) 5254 bwn_core_stop(mac); 5255 if (prev_status >= BWN_MAC_STATUS_INITED) 5256 bwn_core_exit(mac); 5257 5258 if (prev_status >= BWN_MAC_STATUS_INITED) { 5259 error = bwn_core_init(mac); 5260 if (error) 5261 goto out; 5262 } 5263 if (prev_status >= BWN_MAC_STATUS_STARTED) 5264 bwn_core_start(mac); 5265out: 5266 if (error) { 5267 device_printf(sc->sc_dev, "%s: failed (%d)\n", __func__, error); 5268 sc->sc_curmac = NULL; 5269 } 5270 BWN_UNLOCK(sc); 5271} 5272 5273static void 5274bwn_handle_fwpanic(struct bwn_mac *mac) 5275{ 5276 struct bwn_softc *sc = mac->mac_sc; 5277 uint16_t reason; 5278 5279 reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_FWPANIC_REASON_REG); 5280 device_printf(sc->sc_dev,"fw panic (%u)\n", reason); 5281 5282 if (reason == BWN_FWPANIC_RESTART) 5283 bwn_restart(mac, "ucode panic"); 5284} 5285 5286static void 5287bwn_load_beacon0(struct bwn_mac *mac) 5288{ 5289 5290 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 5291} 5292 5293static void 5294bwn_load_beacon1(struct bwn_mac *mac) 5295{ 5296 5297 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 5298} 5299 5300static uint32_t 5301bwn_jssi_read(struct bwn_mac *mac) 5302{ 5303 uint32_t val = 0; 5304 5305 val = bwn_shm_read_2(mac, BWN_SHARED, 0x08a); 5306 val <<= 16; 5307 val |= bwn_shm_read_2(mac, BWN_SHARED, 0x088); 5308 5309 return (val); 5310} 5311 5312static void 5313bwn_noise_gensample(struct bwn_mac *mac) 5314{ 5315 uint32_t jssi = 0x7f7f7f7f; 5316 5317 bwn_shm_write_2(mac, BWN_SHARED, 0x088, (jssi & 0x0000ffff)); 5318 bwn_shm_write_2(mac, BWN_SHARED, 0x08a, (jssi & 0xffff0000) >> 16); 5319 BWN_WRITE_4(mac, BWN_MACCMD, 5320 BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_BGNOISE); 5321} 5322 5323static int 5324bwn_dma_freeslot(struct bwn_dma_ring *dr) 5325{ 5326 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc); 5327 5328 return (dr->dr_numslots - dr->dr_usedslot); 5329} 5330 5331static int 5332bwn_dma_nextslot(struct bwn_dma_ring *dr, int slot) 5333{ 5334 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc); 5335 5336 KASSERT(slot >= -1 && slot <= dr->dr_numslots - 1, 5337 ("%s:%d: fail", __func__, __LINE__)); 5338 if (slot == dr->dr_numslots - 1) 5339 return (0); 5340 return (slot + 1); 5341} 5342 5343static void 5344bwn_dma_rxeof(struct bwn_dma_ring *dr, int *slot) 5345{ 5346 struct bwn_mac *mac = dr->dr_mac; 5347 struct bwn_softc *sc = mac->mac_sc; 5348 struct bwn_dma *dma = &mac->mac_method.dma; 5349 struct bwn_dmadesc_generic *desc; 5350 struct bwn_dmadesc_meta *meta; 5351 struct bwn_rxhdr4 *rxhdr; 5352 struct mbuf *m; 5353 uint32_t macstat; 5354 int32_t tmp; 5355 int cnt = 0; 5356 uint16_t len; 5357 5358 dr->getdesc(dr, *slot, &desc, &meta); 5359 5360 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, BUS_DMASYNC_POSTREAD); 5361 m = meta->mt_m; 5362 5363 if (bwn_dma_newbuf(dr, desc, meta, 0)) { 5364 counter_u64_add(sc->sc_ic.ic_ierrors, 1); 5365 return; 5366 } 5367 5368 rxhdr = mtod(m, struct bwn_rxhdr4 *); 5369 len = le16toh(rxhdr->frame_len); 5370 if (len <= 0) { 5371 counter_u64_add(sc->sc_ic.ic_ierrors, 1); 5372 return; 5373 } 5374 if (bwn_dma_check_redzone(dr, m)) { 5375 device_printf(sc->sc_dev, "redzone error.\n"); 5376 bwn_dma_set_redzone(dr, m); 5377 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, 5378 BUS_DMASYNC_PREWRITE); 5379 return; 5380 } 5381 if (len > dr->dr_rx_bufsize) { 5382 tmp = len; 5383 while (1) { 5384 dr->getdesc(dr, *slot, &desc, &meta); 5385 bwn_dma_set_redzone(dr, meta->mt_m); 5386 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, 5387 BUS_DMASYNC_PREWRITE); 5388 *slot = bwn_dma_nextslot(dr, *slot); 5389 cnt++; 5390 tmp -= dr->dr_rx_bufsize; 5391 if (tmp <= 0) 5392 break; 5393 } 5394 device_printf(sc->sc_dev, "too small buffer " 5395 "(len %u buffer %u dropped %d)\n", 5396 len, dr->dr_rx_bufsize, cnt); 5397 return; 5398 } 5399 5400 switch (mac->mac_fw.fw_hdr_format) { 5401 case BWN_FW_HDR_351: 5402 case BWN_FW_HDR_410: 5403 macstat = le32toh(rxhdr->ps4.r351.mac_status); 5404 break; 5405 case BWN_FW_HDR_598: 5406 macstat = le32toh(rxhdr->ps4.r598.mac_status); 5407 break; 5408 } 5409 5410 if (macstat & BWN_RX_MAC_FCSERR) { 5411 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) { 5412 device_printf(sc->sc_dev, "RX drop\n"); 5413 return; 5414 } 5415 } 5416 5417 m->m_len = m->m_pkthdr.len = len + dr->dr_frameoffset; 5418 m_adj(m, dr->dr_frameoffset); 5419 5420 bwn_rxeof(dr->dr_mac, m, rxhdr); 5421} 5422 5423static void 5424bwn_handle_txeof(struct bwn_mac *mac, const struct bwn_txstatus *status) 5425{ 5426 struct bwn_softc *sc = mac->mac_sc; 5427 struct bwn_stats *stats = &mac->mac_stats; 5428 5429 BWN_ASSERT_LOCKED(mac->mac_sc); 5430 5431 if (status->im) 5432 device_printf(sc->sc_dev, "TODO: STATUS IM\n"); 5433 if (status->ampdu) 5434 device_printf(sc->sc_dev, "TODO: STATUS AMPDU\n"); 5435 if (status->rtscnt) { 5436 if (status->rtscnt == 0xf) 5437 stats->rtsfail++; 5438 else 5439 stats->rts++; 5440 } 5441 5442 if (mac->mac_flags & BWN_MAC_FLAG_DMA) { 5443 bwn_dma_handle_txeof(mac, status); 5444 } else { 5445 bwn_pio_handle_txeof(mac, status); 5446 } 5447 5448 bwn_phy_txpower_check(mac, 0); 5449} 5450 5451static uint8_t 5452bwn_pio_rxeof(struct bwn_pio_rxqueue *prq) 5453{ 5454 struct bwn_mac *mac = prq->prq_mac; 5455 struct bwn_softc *sc = mac->mac_sc; 5456 struct bwn_rxhdr4 rxhdr; 5457 struct mbuf *m; 5458 uint32_t ctl32, macstat, v32; 5459 unsigned int i, padding; 5460 uint16_t ctl16, len, totlen, v16; 5461 unsigned char *mp; 5462 char *data; 5463 5464 memset(&rxhdr, 0, sizeof(rxhdr)); 5465 5466 if (prq->prq_rev >= 8) { 5467 ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL); 5468 if (!(ctl32 & BWN_PIO8_RXCTL_FRAMEREADY)) 5469 return (0); 5470 bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL, 5471 BWN_PIO8_RXCTL_FRAMEREADY); 5472 for (i = 0; i < 10; i++) { 5473 ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL); 5474 if (ctl32 & BWN_PIO8_RXCTL_DATAREADY) 5475 goto ready; 5476 DELAY(10); 5477 } 5478 } else { 5479 ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL); 5480 if (!(ctl16 & BWN_PIO_RXCTL_FRAMEREADY)) 5481 return (0); 5482 bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL, 5483 BWN_PIO_RXCTL_FRAMEREADY); 5484 for (i = 0; i < 10; i++) { 5485 ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL); 5486 if (ctl16 & BWN_PIO_RXCTL_DATAREADY) 5487 goto ready; 5488 DELAY(10); 5489 } 5490 } 5491 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 5492 return (1); 5493ready: 5494 if (prq->prq_rev >= 8) 5495 siba_read_multi_4(sc->sc_dev, &rxhdr, sizeof(rxhdr), 5496 prq->prq_base + BWN_PIO8_RXDATA); 5497 else 5498 siba_read_multi_2(sc->sc_dev, &rxhdr, sizeof(rxhdr), 5499 prq->prq_base + BWN_PIO_RXDATA); 5500 len = le16toh(rxhdr.frame_len); 5501 if (len > 0x700) { 5502 device_printf(sc->sc_dev, "%s: len is too big\n", __func__); 5503 goto error; 5504 } 5505 if (len == 0) { 5506 device_printf(sc->sc_dev, "%s: len is 0\n", __func__); 5507 goto error; 5508 } 5509 5510 switch (mac->mac_fw.fw_hdr_format) { 5511 case BWN_FW_HDR_351: 5512 case BWN_FW_HDR_410: 5513 macstat = le32toh(rxhdr.ps4.r351.mac_status); 5514 break; 5515 case BWN_FW_HDR_598: 5516 macstat = le32toh(rxhdr.ps4.r598.mac_status); 5517 break; 5518 } 5519 5520 if (macstat & BWN_RX_MAC_FCSERR) { 5521 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) { 5522 device_printf(sc->sc_dev, "%s: FCS error", __func__); 5523 goto error; 5524 } 5525 } 5526 5527 padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0; 5528 totlen = len + padding; 5529 KASSERT(totlen <= MCLBYTES, ("too big..\n")); 5530 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 5531 if (m == NULL) { 5532 device_printf(sc->sc_dev, "%s: out of memory", __func__); 5533 goto error; 5534 } 5535 mp = mtod(m, unsigned char *); 5536 if (prq->prq_rev >= 8) { 5537 siba_read_multi_4(sc->sc_dev, mp, (totlen & ~3), 5538 prq->prq_base + BWN_PIO8_RXDATA); 5539 if (totlen & 3) { 5540 v32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXDATA); 5541 data = &(mp[totlen - 1]); 5542 switch (totlen & 3) { 5543 case 3: 5544 *data = (v32 >> 16); 5545 data--; 5546 case 2: 5547 *data = (v32 >> 8); 5548 data--; 5549 case 1: 5550 *data = v32; 5551 } 5552 } 5553 } else { 5554 siba_read_multi_2(sc->sc_dev, mp, (totlen & ~1), 5555 prq->prq_base + BWN_PIO_RXDATA); 5556 if (totlen & 1) { 5557 v16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXDATA); 5558 mp[totlen - 1] = v16; 5559 } 5560 } 5561 5562 m->m_len = m->m_pkthdr.len = totlen; 5563 5564 bwn_rxeof(prq->prq_mac, m, &rxhdr); 5565 5566 return (1); 5567error: 5568 if (prq->prq_rev >= 8) 5569 bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL, 5570 BWN_PIO8_RXCTL_DATAREADY); 5571 else 5572 bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL, BWN_PIO_RXCTL_DATAREADY); 5573 return (1); 5574} 5575 5576static int 5577bwn_dma_newbuf(struct bwn_dma_ring *dr, struct bwn_dmadesc_generic *desc, 5578 struct bwn_dmadesc_meta *meta, int init) 5579{ 5580 struct bwn_mac *mac = dr->dr_mac; 5581 struct bwn_dma *dma = &mac->mac_method.dma; 5582 struct bwn_rxhdr4 *hdr; 5583 bus_dmamap_t map; 5584 bus_addr_t paddr; 5585 struct mbuf *m; 5586 int error; 5587 5588 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 5589 if (m == NULL) { 5590 error = ENOBUFS; 5591 5592 /* 5593 * If the NIC is up and running, we need to: 5594 * - Clear RX buffer's header. 5595 * - Restore RX descriptor settings. 5596 */ 5597 if (init) 5598 return (error); 5599 else 5600 goto back; 5601 } 5602 m->m_len = m->m_pkthdr.len = MCLBYTES; 5603 5604 bwn_dma_set_redzone(dr, m); 5605 5606 /* 5607 * Try to load RX buf into temporary DMA map 5608 */ 5609 error = bus_dmamap_load_mbuf(dma->rxbuf_dtag, dr->dr_spare_dmap, m, 5610 bwn_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 5611 if (error) { 5612 m_freem(m); 5613 5614 /* 5615 * See the comment above 5616 */ 5617 if (init) 5618 return (error); 5619 else 5620 goto back; 5621 } 5622 5623 if (!init) 5624 bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap); 5625 meta->mt_m = m; 5626 meta->mt_paddr = paddr; 5627 5628 /* 5629 * Swap RX buf's DMA map with the loaded temporary one 5630 */ 5631 map = meta->mt_dmap; 5632 meta->mt_dmap = dr->dr_spare_dmap; 5633 dr->dr_spare_dmap = map; 5634 5635back: 5636 /* 5637 * Clear RX buf header 5638 */ 5639 hdr = mtod(meta->mt_m, struct bwn_rxhdr4 *); 5640 bzero(hdr, sizeof(*hdr)); 5641 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, 5642 BUS_DMASYNC_PREWRITE); 5643 5644 /* 5645 * Setup RX buf descriptor 5646 */ 5647 dr->setdesc(dr, desc, meta->mt_paddr, meta->mt_m->m_len - 5648 sizeof(*hdr), 0, 0, 0); 5649 return (error); 5650} 5651 5652static void 5653bwn_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 5654 bus_size_t mapsz __unused, int error) 5655{ 5656 5657 if (!error) { 5658 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 5659 *((bus_addr_t *)arg) = seg->ds_addr; 5660 } 5661} 5662 5663static int 5664bwn_hwrate2ieeerate(int rate) 5665{ 5666 5667 switch (rate) { 5668 case BWN_CCK_RATE_1MB: 5669 return (2); 5670 case BWN_CCK_RATE_2MB: 5671 return (4); 5672 case BWN_CCK_RATE_5MB: 5673 return (11); 5674 case BWN_CCK_RATE_11MB: 5675 return (22); 5676 case BWN_OFDM_RATE_6MB: 5677 return (12); 5678 case BWN_OFDM_RATE_9MB: 5679 return (18); 5680 case BWN_OFDM_RATE_12MB: 5681 return (24); 5682 case BWN_OFDM_RATE_18MB: 5683 return (36); 5684 case BWN_OFDM_RATE_24MB: 5685 return (48); 5686 case BWN_OFDM_RATE_36MB: 5687 return (72); 5688 case BWN_OFDM_RATE_48MB: 5689 return (96); 5690 case BWN_OFDM_RATE_54MB: 5691 return (108); 5692 default: 5693 printf("Ooops\n"); 5694 return (0); 5695 } 5696} 5697 5698/* 5699 * Post process the RX provided RSSI. 5700 * 5701 * Valid for A, B, G, LP PHYs. 5702 */ 5703static int8_t 5704bwn_rx_rssi_calc(struct bwn_mac *mac, uint8_t in_rssi, 5705 int ofdm, int adjust_2053, int adjust_2050) 5706{ 5707 struct bwn_phy *phy = &mac->mac_phy; 5708 struct bwn_phy_g *gphy = &phy->phy_g; 5709 int tmp; 5710 5711 switch (phy->rf_ver) { 5712 case 0x2050: 5713 if (ofdm) { 5714 tmp = in_rssi; 5715 if (tmp > 127) 5716 tmp -= 256; 5717 tmp = tmp * 73 / 64; 5718 if (adjust_2050) 5719 tmp += 25; 5720 else 5721 tmp -= 3; 5722 } else { 5723 if (siba_sprom_get_bf_lo(mac->mac_sc->sc_dev) 5724 & BWN_BFL_RSSI) { 5725 if (in_rssi > 63) 5726 in_rssi = 63; 5727 tmp = gphy->pg_nrssi_lt[in_rssi]; 5728 tmp = (31 - tmp) * -131 / 128 - 57; 5729 } else { 5730 tmp = in_rssi; 5731 tmp = (31 - tmp) * -149 / 128 - 68; 5732 } 5733 if (phy->type == BWN_PHYTYPE_G && adjust_2050) 5734 tmp += 25; 5735 } 5736 break; 5737 case 0x2060: 5738 if (in_rssi > 127) 5739 tmp = in_rssi - 256; 5740 else 5741 tmp = in_rssi; 5742 break; 5743 default: 5744 tmp = in_rssi; 5745 tmp = (tmp - 11) * 103 / 64; 5746 if (adjust_2053) 5747 tmp -= 109; 5748 else 5749 tmp -= 83; 5750 } 5751 5752 return (tmp); 5753} 5754 5755static void 5756bwn_rxeof(struct bwn_mac *mac, struct mbuf *m, const void *_rxhdr) 5757{ 5758 const struct bwn_rxhdr4 *rxhdr = _rxhdr; 5759 struct bwn_plcp6 *plcp; 5760 struct bwn_softc *sc = mac->mac_sc; 5761 struct ieee80211_frame_min *wh; 5762 struct ieee80211_node *ni; 5763 struct ieee80211com *ic = &sc->sc_ic; 5764 uint32_t macstat; 5765 int padding, rate, rssi = 0, noise = 0, type; 5766 uint16_t phytype, phystat0, phystat3, chanstat; 5767 unsigned char *mp = mtod(m, unsigned char *); 5768 static int rx_mac_dec_rpt = 0; 5769 5770 BWN_ASSERT_LOCKED(sc); 5771 5772 phystat0 = le16toh(rxhdr->phy_status0); 5773 5774 /* 5775 * XXX Note: phy_status3 doesn't exist for HT-PHY; it's only 5776 * used for LP-PHY. 5777 */ 5778 phystat3 = le16toh(rxhdr->ps3.lp.phy_status3); 5779 5780 switch (mac->mac_fw.fw_hdr_format) { 5781 case BWN_FW_HDR_351: 5782 case BWN_FW_HDR_410: 5783 macstat = le32toh(rxhdr->ps4.r351.mac_status); 5784 chanstat = le16toh(rxhdr->ps4.r351.channel); 5785 break; 5786 case BWN_FW_HDR_598: 5787 macstat = le32toh(rxhdr->ps4.r598.mac_status); 5788 chanstat = le16toh(rxhdr->ps4.r598.channel); 5789 break; 5790 } 5791 5792 5793 phytype = chanstat & BWN_RX_CHAN_PHYTYPE; 5794 5795 if (macstat & BWN_RX_MAC_FCSERR) 5796 device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_FCS_CRC\n"); 5797 if (phystat0 & (BWN_RX_PHYST0_PLCPHCF | BWN_RX_PHYST0_PLCPFV)) 5798 device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_PLCP_CRC\n"); 5799 if (macstat & BWN_RX_MAC_DECERR) 5800 goto drop; 5801 5802 padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0; 5803 if (m->m_pkthdr.len < (sizeof(struct bwn_plcp6) + padding)) { 5804 device_printf(sc->sc_dev, "frame too short (length=%d)\n", 5805 m->m_pkthdr.len); 5806 goto drop; 5807 } 5808 plcp = (struct bwn_plcp6 *)(mp + padding); 5809 m_adj(m, sizeof(struct bwn_plcp6) + padding); 5810 if (m->m_pkthdr.len < IEEE80211_MIN_LEN) { 5811 device_printf(sc->sc_dev, "frame too short (length=%d)\n", 5812 m->m_pkthdr.len); 5813 goto drop; 5814 } 5815 wh = mtod(m, struct ieee80211_frame_min *); 5816 5817 if (macstat & BWN_RX_MAC_DEC && rx_mac_dec_rpt++ < 50) 5818 device_printf(sc->sc_dev, 5819 "RX decryption attempted (old %d keyidx %#x)\n", 5820 BWN_ISOLDFMT(mac), 5821 (macstat & BWN_RX_MAC_KEYIDX) >> BWN_RX_MAC_KEYIDX_SHIFT); 5822 5823 if (phystat0 & BWN_RX_PHYST0_OFDM) 5824 rate = bwn_plcp_get_ofdmrate(mac, plcp, 5825 phytype == BWN_PHYTYPE_A); 5826 else 5827 rate = bwn_plcp_get_cckrate(mac, plcp); 5828 if (rate == -1) { 5829 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADPLCP)) 5830 goto drop; 5831 } 5832 sc->sc_rx_rate = bwn_hwrate2ieeerate(rate); 5833 5834 /* rssi/noise */ 5835 switch (phytype) { 5836 case BWN_PHYTYPE_A: 5837 case BWN_PHYTYPE_B: 5838 case BWN_PHYTYPE_G: 5839 case BWN_PHYTYPE_LP: 5840 rssi = bwn_rx_rssi_calc(mac, rxhdr->phy.abg.rssi, 5841 !! (phystat0 & BWN_RX_PHYST0_OFDM), 5842 !! (phystat0 & BWN_RX_PHYST0_GAINCTL), 5843 !! (phystat3 & BWN_RX_PHYST3_TRSTATE)); 5844 break; 5845 case BWN_PHYTYPE_N: 5846 /* Broadcom has code for min/avg, but always used max */ 5847 if (rxhdr->phy.n.power0 == 16 || rxhdr->phy.n.power0 == 32) 5848 rssi = max(rxhdr->phy.n.power1, rxhdr->ps2.n.power2); 5849 else 5850 rssi = max(rxhdr->phy.n.power0, rxhdr->phy.n.power1); 5851#if 0 5852 DPRINTF(mac->mac_sc, BWN_DEBUG_RECV, 5853 "%s: power0=%d, power1=%d, power2=%d\n", 5854 __func__, 5855 rxhdr->phy.n.power0, 5856 rxhdr->phy.n.power1, 5857 rxhdr->ps2.n.power2); 5858#endif 5859 break; 5860 default: 5861 /* XXX TODO: implement rssi for other PHYs */ 5862 break; 5863 } 5864 5865 /* 5866 * RSSI here is absolute, not relative to the noise floor. 5867 */ 5868 noise = mac->mac_stats.link_noise; 5869 rssi = rssi - noise; 5870 5871 /* RX radio tap */ 5872 if (ieee80211_radiotap_active(ic)) 5873 bwn_rx_radiotap(mac, m, rxhdr, plcp, rate, rssi, noise); 5874 m_adj(m, -IEEE80211_CRC_LEN); 5875 5876 BWN_UNLOCK(sc); 5877 5878 ni = ieee80211_find_rxnode(ic, wh); 5879 if (ni != NULL) { 5880 type = ieee80211_input(ni, m, rssi, noise); 5881 ieee80211_free_node(ni); 5882 } else 5883 type = ieee80211_input_all(ic, m, rssi, noise); 5884 5885 BWN_LOCK(sc); 5886 return; 5887drop: 5888 device_printf(sc->sc_dev, "%s: dropped\n", __func__); 5889} 5890 5891static void 5892bwn_dma_handle_txeof(struct bwn_mac *mac, 5893 const struct bwn_txstatus *status) 5894{ 5895 struct bwn_dma *dma = &mac->mac_method.dma; 5896 struct bwn_dma_ring *dr; 5897 struct bwn_dmadesc_generic *desc; 5898 struct bwn_dmadesc_meta *meta; 5899 struct bwn_softc *sc = mac->mac_sc; 5900 int slot; 5901 int retrycnt = 0; 5902 5903 BWN_ASSERT_LOCKED(sc); 5904 5905 dr = bwn_dma_parse_cookie(mac, status, status->cookie, &slot); 5906 if (dr == NULL) { 5907 device_printf(sc->sc_dev, "failed to parse cookie\n"); 5908 return; 5909 } 5910 KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__)); 5911 5912 while (1) { 5913 KASSERT(slot >= 0 && slot < dr->dr_numslots, 5914 ("%s:%d: fail", __func__, __LINE__)); 5915 dr->getdesc(dr, slot, &desc, &meta); 5916 5917 if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER) 5918 bus_dmamap_unload(dr->dr_txring_dtag, meta->mt_dmap); 5919 else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY) 5920 bus_dmamap_unload(dma->txbuf_dtag, meta->mt_dmap); 5921 5922 if (meta->mt_islast) { 5923 KASSERT(meta->mt_m != NULL, 5924 ("%s:%d: fail", __func__, __LINE__)); 5925 5926 /* 5927 * If we don't get an ACK, then we should log the 5928 * full framecnt. That may be 0 if it's a PHY 5929 * failure, so ensure that gets logged as some 5930 * retry attempt. 5931 */ 5932 if (status->ack) { 5933 retrycnt = status->framecnt - 1; 5934 } else { 5935 retrycnt = status->framecnt; 5936 if (retrycnt == 0) 5937 retrycnt = 1; 5938 } 5939 ieee80211_ratectl_tx_complete(meta->mt_ni->ni_vap, meta->mt_ni, 5940 status->ack ? 5941 IEEE80211_RATECTL_TX_SUCCESS : 5942 IEEE80211_RATECTL_TX_FAILURE, 5943 &retrycnt, 0); 5944 ieee80211_tx_complete(meta->mt_ni, meta->mt_m, 0); 5945 meta->mt_ni = NULL; 5946 meta->mt_m = NULL; 5947 } else 5948 KASSERT(meta->mt_m == NULL, 5949 ("%s:%d: fail", __func__, __LINE__)); 5950 5951 dr->dr_usedslot--; 5952 if (meta->mt_islast) 5953 break; 5954 slot = bwn_dma_nextslot(dr, slot); 5955 } 5956 sc->sc_watchdog_timer = 0; 5957 if (dr->dr_stop) { 5958 KASSERT(bwn_dma_freeslot(dr) >= BWN_TX_SLOTS_PER_FRAME, 5959 ("%s:%d: fail", __func__, __LINE__)); 5960 dr->dr_stop = 0; 5961 } 5962} 5963 5964static void 5965bwn_pio_handle_txeof(struct bwn_mac *mac, 5966 const struct bwn_txstatus *status) 5967{ 5968 struct bwn_pio_txqueue *tq; 5969 struct bwn_pio_txpkt *tp = NULL; 5970 struct bwn_softc *sc = mac->mac_sc; 5971 int retrycnt = 0; 5972 5973 BWN_ASSERT_LOCKED(sc); 5974 5975 tq = bwn_pio_parse_cookie(mac, status->cookie, &tp); 5976 if (tq == NULL) 5977 return; 5978 5979 tq->tq_used -= roundup(tp->tp_m->m_pkthdr.len + BWN_HDRSIZE(mac), 4); 5980 tq->tq_free++; 5981 5982 if (tp->tp_ni != NULL) { 5983 /* 5984 * Do any tx complete callback. Note this must 5985 * be done before releasing the node reference. 5986 */ 5987 /* 5988 * If we don't get an ACK, then we should log the 5989 * full framecnt. That may be 0 if it's a PHY 5990 * failure, so ensure that gets logged as some 5991 * retry attempt. 5992 */ 5993 if (status->ack) { 5994 retrycnt = status->framecnt - 1; 5995 } else { 5996 retrycnt = status->framecnt; 5997 if (retrycnt == 0) 5998 retrycnt = 1; 5999 } 6000 ieee80211_ratectl_tx_complete(tp->tp_ni->ni_vap, tp->tp_ni, 6001 status->ack ? 6002 IEEE80211_RATECTL_TX_SUCCESS : 6003 IEEE80211_RATECTL_TX_FAILURE, 6004 &retrycnt, 0); 6005 6006 } 6007 ieee80211_tx_complete(tp->tp_ni, tp->tp_m, 0); 6008 tp->tp_ni = NULL; 6009 tp->tp_m = NULL; 6010 TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list); 6011 6012 sc->sc_watchdog_timer = 0; 6013} 6014 6015static void 6016bwn_phy_txpower_check(struct bwn_mac *mac, uint32_t flags) 6017{ 6018 struct bwn_softc *sc = mac->mac_sc; 6019 struct bwn_phy *phy = &mac->mac_phy; 6020 struct ieee80211com *ic = &sc->sc_ic; 6021 unsigned long now; 6022 bwn_txpwr_result_t result; 6023 6024 BWN_GETTIME(now); 6025 6026 if (!(flags & BWN_TXPWR_IGNORE_TIME) && ieee80211_time_before(now, phy->nexttime)) 6027 return; 6028 phy->nexttime = now + 2 * 1000; 6029 6030 if (siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM && 6031 siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BU4306) 6032 return; 6033 6034 if (phy->recalc_txpwr != NULL) { 6035 result = phy->recalc_txpwr(mac, 6036 (flags & BWN_TXPWR_IGNORE_TSSI) ? 1 : 0); 6037 if (result == BWN_TXPWR_RES_DONE) 6038 return; 6039 KASSERT(result == BWN_TXPWR_RES_NEED_ADJUST, 6040 ("%s: fail", __func__)); 6041 KASSERT(phy->set_txpwr != NULL, ("%s: fail", __func__)); 6042 6043 ieee80211_runtask(ic, &mac->mac_txpower); 6044 } 6045} 6046 6047static uint16_t 6048bwn_pio_rx_read_2(struct bwn_pio_rxqueue *prq, uint16_t offset) 6049{ 6050 6051 return (BWN_READ_2(prq->prq_mac, prq->prq_base + offset)); 6052} 6053 6054static uint32_t 6055bwn_pio_rx_read_4(struct bwn_pio_rxqueue *prq, uint16_t offset) 6056{ 6057 6058 return (BWN_READ_4(prq->prq_mac, prq->prq_base + offset)); 6059} 6060 6061static void 6062bwn_pio_rx_write_2(struct bwn_pio_rxqueue *prq, uint16_t offset, uint16_t value) 6063{ 6064 6065 BWN_WRITE_2(prq->prq_mac, prq->prq_base + offset, value); 6066} 6067 6068static void 6069bwn_pio_rx_write_4(struct bwn_pio_rxqueue *prq, uint16_t offset, uint32_t value) 6070{ 6071 6072 BWN_WRITE_4(prq->prq_mac, prq->prq_base + offset, value); 6073} 6074 6075static int 6076bwn_ieeerate2hwrate(struct bwn_softc *sc, int rate) 6077{ 6078 6079 switch (rate) { 6080 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 6081 case 12: 6082 return (BWN_OFDM_RATE_6MB); 6083 case 18: 6084 return (BWN_OFDM_RATE_9MB); 6085 case 24: 6086 return (BWN_OFDM_RATE_12MB); 6087 case 36: 6088 return (BWN_OFDM_RATE_18MB); 6089 case 48: 6090 return (BWN_OFDM_RATE_24MB); 6091 case 72: 6092 return (BWN_OFDM_RATE_36MB); 6093 case 96: 6094 return (BWN_OFDM_RATE_48MB); 6095 case 108: 6096 return (BWN_OFDM_RATE_54MB); 6097 /* CCK rates (NB: not IEEE std, device-specific) */ 6098 case 2: 6099 return (BWN_CCK_RATE_1MB); 6100 case 4: 6101 return (BWN_CCK_RATE_2MB); 6102 case 11: 6103 return (BWN_CCK_RATE_5MB); 6104 case 22: 6105 return (BWN_CCK_RATE_11MB); 6106 } 6107 6108 device_printf(sc->sc_dev, "unsupported rate %d\n", rate); 6109 return (BWN_CCK_RATE_1MB); 6110} 6111 6112static uint16_t 6113bwn_set_txhdr_phyctl1(struct bwn_mac *mac, uint8_t bitrate) 6114{ 6115 struct bwn_phy *phy = &mac->mac_phy; 6116 uint16_t control = 0; 6117 uint16_t bw; 6118 6119 /* XXX TODO: this is for LP phy, what about N-PHY, etc? */ 6120 bw = BWN_TXH_PHY1_BW_20; 6121 6122 if (BWN_ISCCKRATE(bitrate) && phy->type != BWN_PHYTYPE_LP) { 6123 control = bw; 6124 } else { 6125 control = bw; 6126 /* Figure out coding rate and modulation */ 6127 /* XXX TODO: table-ize, for MCS transmit */ 6128 /* Note: this is BWN_*_RATE values */ 6129 switch (bitrate) { 6130 case BWN_CCK_RATE_1MB: 6131 control |= 0; 6132 break; 6133 case BWN_CCK_RATE_2MB: 6134 control |= 1; 6135 break; 6136 case BWN_CCK_RATE_5MB: 6137 control |= 2; 6138 break; 6139 case BWN_CCK_RATE_11MB: 6140 control |= 3; 6141 break; 6142 case BWN_OFDM_RATE_6MB: 6143 control |= BWN_TXH_PHY1_CRATE_1_2; 6144 control |= BWN_TXH_PHY1_MODUL_BPSK; 6145 break; 6146 case BWN_OFDM_RATE_9MB: 6147 control |= BWN_TXH_PHY1_CRATE_3_4; 6148 control |= BWN_TXH_PHY1_MODUL_BPSK; 6149 break; 6150 case BWN_OFDM_RATE_12MB: 6151 control |= BWN_TXH_PHY1_CRATE_1_2; 6152 control |= BWN_TXH_PHY1_MODUL_QPSK; 6153 break; 6154 case BWN_OFDM_RATE_18MB: 6155 control |= BWN_TXH_PHY1_CRATE_3_4; 6156 control |= BWN_TXH_PHY1_MODUL_QPSK; 6157 break; 6158 case BWN_OFDM_RATE_24MB: 6159 control |= BWN_TXH_PHY1_CRATE_1_2; 6160 control |= BWN_TXH_PHY1_MODUL_QAM16; 6161 break; 6162 case BWN_OFDM_RATE_36MB: 6163 control |= BWN_TXH_PHY1_CRATE_3_4; 6164 control |= BWN_TXH_PHY1_MODUL_QAM16; 6165 break; 6166 case BWN_OFDM_RATE_48MB: 6167 control |= BWN_TXH_PHY1_CRATE_1_2; 6168 control |= BWN_TXH_PHY1_MODUL_QAM64; 6169 break; 6170 case BWN_OFDM_RATE_54MB: 6171 control |= BWN_TXH_PHY1_CRATE_3_4; 6172 control |= BWN_TXH_PHY1_MODUL_QAM64; 6173 break; 6174 default: 6175 break; 6176 } 6177 control |= BWN_TXH_PHY1_MODE_SISO; 6178 } 6179 6180 return control; 6181} 6182 6183static int 6184bwn_set_txhdr(struct bwn_mac *mac, struct ieee80211_node *ni, 6185 struct mbuf *m, struct bwn_txhdr *txhdr, uint16_t cookie) 6186{ 6187 const struct bwn_phy *phy = &mac->mac_phy; 6188 struct bwn_softc *sc = mac->mac_sc; 6189 struct ieee80211_frame *wh; 6190 struct ieee80211_frame *protwh; 6191 struct ieee80211_frame_cts *cts; 6192 struct ieee80211_frame_rts *rts; 6193 const struct ieee80211_txparam *tp; 6194 struct ieee80211vap *vap = ni->ni_vap; 6195 struct ieee80211com *ic = &sc->sc_ic; 6196 struct mbuf *mprot; 6197 unsigned int len; 6198 uint32_t macctl = 0; 6199 int protdur, rts_rate, rts_rate_fb, ismcast, isshort, rix, type; 6200 uint16_t phyctl = 0; 6201 uint8_t rate, rate_fb; 6202 int fill_phy_ctl1 = 0; 6203 6204 wh = mtod(m, struct ieee80211_frame *); 6205 memset(txhdr, 0, sizeof(*txhdr)); 6206 6207 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 6208 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 6209 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 6210 6211 if ((phy->type == BWN_PHYTYPE_N) || (phy->type == BWN_PHYTYPE_LP) 6212 || (phy->type == BWN_PHYTYPE_HT)) 6213 fill_phy_ctl1 = 1; 6214 6215 /* 6216 * Find TX rate 6217 */ 6218 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 6219 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) 6220 rate = rate_fb = tp->mgmtrate; 6221 else if (ismcast) 6222 rate = rate_fb = tp->mcastrate; 6223 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 6224 rate = rate_fb = tp->ucastrate; 6225 else { 6226 rix = ieee80211_ratectl_rate(ni, NULL, 0); 6227 rate = ni->ni_txrate; 6228 6229 if (rix > 0) 6230 rate_fb = ni->ni_rates.rs_rates[rix - 1] & 6231 IEEE80211_RATE_VAL; 6232 else 6233 rate_fb = rate; 6234 } 6235 6236 sc->sc_tx_rate = rate; 6237 6238 /* Note: this maps the select ieee80211 rate to hardware rate */ 6239 rate = bwn_ieeerate2hwrate(sc, rate); 6240 rate_fb = bwn_ieeerate2hwrate(sc, rate_fb); 6241 6242 txhdr->phyrate = (BWN_ISOFDMRATE(rate)) ? bwn_plcp_getofdm(rate) : 6243 bwn_plcp_getcck(rate); 6244 bcopy(wh->i_fc, txhdr->macfc, sizeof(txhdr->macfc)); 6245 bcopy(wh->i_addr1, txhdr->addr1, IEEE80211_ADDR_LEN); 6246 6247 /* XXX rate/rate_fb is the hardware rate */ 6248 if ((rate_fb == rate) || 6249 (*(u_int16_t *)wh->i_dur & htole16(0x8000)) || 6250 (*(u_int16_t *)wh->i_dur == htole16(0))) 6251 txhdr->dur_fb = *(u_int16_t *)wh->i_dur; 6252 else 6253 txhdr->dur_fb = ieee80211_compute_duration(ic->ic_rt, 6254 m->m_pkthdr.len, rate, isshort); 6255 6256 /* XXX TX encryption */ 6257 6258 switch (mac->mac_fw.fw_hdr_format) { 6259 case BWN_FW_HDR_351: 6260 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r351.plcp), 6261 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); 6262 break; 6263 case BWN_FW_HDR_410: 6264 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r410.plcp), 6265 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); 6266 break; 6267 case BWN_FW_HDR_598: 6268 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r598.plcp), 6269 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); 6270 break; 6271 } 6272 6273 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->plcp_fb), 6274 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate_fb); 6275 6276 txhdr->eftypes |= (BWN_ISOFDMRATE(rate_fb)) ? BWN_TX_EFT_FB_OFDM : 6277 BWN_TX_EFT_FB_CCK; 6278 txhdr->chan = phy->chan; 6279 phyctl |= (BWN_ISOFDMRATE(rate)) ? BWN_TX_PHY_ENC_OFDM : 6280 BWN_TX_PHY_ENC_CCK; 6281 /* XXX preamble? obey net80211 */ 6282 if (isshort && (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB || 6283 rate == BWN_CCK_RATE_11MB)) 6284 phyctl |= BWN_TX_PHY_SHORTPRMBL; 6285 6286 if (! phy->gmode) 6287 macctl |= BWN_TX_MAC_5GHZ; 6288 6289 /* XXX TX antenna selection */ 6290 6291 switch (bwn_antenna_sanitize(mac, 0)) { 6292 case 0: 6293 phyctl |= BWN_TX_PHY_ANT01AUTO; 6294 break; 6295 case 1: 6296 phyctl |= BWN_TX_PHY_ANT0; 6297 break; 6298 case 2: 6299 phyctl |= BWN_TX_PHY_ANT1; 6300 break; 6301 case 3: 6302 phyctl |= BWN_TX_PHY_ANT2; 6303 break; 6304 case 4: 6305 phyctl |= BWN_TX_PHY_ANT3; 6306 break; 6307 default: 6308 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 6309 } 6310 6311 if (!ismcast) 6312 macctl |= BWN_TX_MAC_ACK; 6313 6314 macctl |= (BWN_TX_MAC_HWSEQ | BWN_TX_MAC_START_MSDU); 6315 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 6316 m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 6317 macctl |= BWN_TX_MAC_LONGFRAME; 6318 6319 if (ic->ic_flags & IEEE80211_F_USEPROT) { 6320 /* Note: don't fall back to CCK rates for 5G */ 6321 if (phy->gmode) 6322 rts_rate = BWN_CCK_RATE_1MB; 6323 else 6324 rts_rate = BWN_OFDM_RATE_6MB; 6325 rts_rate_fb = bwn_get_fbrate(rts_rate); 6326 6327 /* XXX 'rate' here is hardware rate now, not the net80211 rate */ 6328 protdur = ieee80211_compute_duration(ic->ic_rt, 6329 m->m_pkthdr.len, rate, isshort) + 6330 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 6331 6332 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 6333 6334 switch (mac->mac_fw.fw_hdr_format) { 6335 case BWN_FW_HDR_351: 6336 cts = (struct ieee80211_frame_cts *) 6337 txhdr->body.r351.rts_frame; 6338 break; 6339 case BWN_FW_HDR_410: 6340 cts = (struct ieee80211_frame_cts *) 6341 txhdr->body.r410.rts_frame; 6342 break; 6343 case BWN_FW_HDR_598: 6344 cts = (struct ieee80211_frame_cts *) 6345 txhdr->body.r598.rts_frame; 6346 break; 6347 } 6348 6349 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, 6350 protdur); 6351 KASSERT(mprot != NULL, ("failed to alloc mbuf\n")); 6352 bcopy(mtod(mprot, uint8_t *), (uint8_t *)cts, 6353 mprot->m_pkthdr.len); 6354 m_freem(mprot); 6355 macctl |= BWN_TX_MAC_SEND_CTSTOSELF; 6356 len = sizeof(struct ieee80211_frame_cts); 6357 } else { 6358 switch (mac->mac_fw.fw_hdr_format) { 6359 case BWN_FW_HDR_351: 6360 rts = (struct ieee80211_frame_rts *) 6361 txhdr->body.r351.rts_frame; 6362 break; 6363 case BWN_FW_HDR_410: 6364 rts = (struct ieee80211_frame_rts *) 6365 txhdr->body.r410.rts_frame; 6366 break; 6367 case BWN_FW_HDR_598: 6368 rts = (struct ieee80211_frame_rts *) 6369 txhdr->body.r598.rts_frame; 6370 break; 6371 } 6372 6373 /* XXX rate/rate_fb is the hardware rate */ 6374 protdur += ieee80211_ack_duration(ic->ic_rt, rate, 6375 isshort); 6376 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, 6377 wh->i_addr2, protdur); 6378 KASSERT(mprot != NULL, ("failed to alloc mbuf\n")); 6379 bcopy(mtod(mprot, uint8_t *), (uint8_t *)rts, 6380 mprot->m_pkthdr.len); 6381 m_freem(mprot); 6382 macctl |= BWN_TX_MAC_SEND_RTSCTS; 6383 len = sizeof(struct ieee80211_frame_rts); 6384 } 6385 len += IEEE80211_CRC_LEN; 6386 6387 switch (mac->mac_fw.fw_hdr_format) { 6388 case BWN_FW_HDR_351: 6389 bwn_plcp_genhdr((struct bwn_plcp4 *) 6390 &txhdr->body.r351.rts_plcp, len, rts_rate); 6391 break; 6392 case BWN_FW_HDR_410: 6393 bwn_plcp_genhdr((struct bwn_plcp4 *) 6394 &txhdr->body.r410.rts_plcp, len, rts_rate); 6395 break; 6396 case BWN_FW_HDR_598: 6397 bwn_plcp_genhdr((struct bwn_plcp4 *) 6398 &txhdr->body.r598.rts_plcp, len, rts_rate); 6399 break; 6400 } 6401 6402 bwn_plcp_genhdr((struct bwn_plcp4 *)&txhdr->rts_plcp_fb, len, 6403 rts_rate_fb); 6404 6405 switch (mac->mac_fw.fw_hdr_format) { 6406 case BWN_FW_HDR_351: 6407 protwh = (struct ieee80211_frame *) 6408 &txhdr->body.r351.rts_frame; 6409 break; 6410 case BWN_FW_HDR_410: 6411 protwh = (struct ieee80211_frame *) 6412 &txhdr->body.r410.rts_frame; 6413 break; 6414 case BWN_FW_HDR_598: 6415 protwh = (struct ieee80211_frame *) 6416 &txhdr->body.r598.rts_frame; 6417 break; 6418 } 6419 6420 txhdr->rts_dur_fb = *(u_int16_t *)protwh->i_dur; 6421 6422 if (BWN_ISOFDMRATE(rts_rate)) { 6423 txhdr->eftypes |= BWN_TX_EFT_RTS_OFDM; 6424 txhdr->phyrate_rts = bwn_plcp_getofdm(rts_rate); 6425 } else { 6426 txhdr->eftypes |= BWN_TX_EFT_RTS_CCK; 6427 txhdr->phyrate_rts = bwn_plcp_getcck(rts_rate); 6428 } 6429 txhdr->eftypes |= (BWN_ISOFDMRATE(rts_rate_fb)) ? 6430 BWN_TX_EFT_RTS_FBOFDM : BWN_TX_EFT_RTS_FBCCK; 6431 6432 if (fill_phy_ctl1) { 6433 txhdr->phyctl_1rts = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate)); 6434 txhdr->phyctl_1rtsfb = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate_fb)); 6435 } 6436 } 6437 6438 if (fill_phy_ctl1) { 6439 txhdr->phyctl_1 = htole16(bwn_set_txhdr_phyctl1(mac, rate)); 6440 txhdr->phyctl_1fb = htole16(bwn_set_txhdr_phyctl1(mac, rate_fb)); 6441 } 6442 6443 switch (mac->mac_fw.fw_hdr_format) { 6444 case BWN_FW_HDR_351: 6445 txhdr->body.r351.cookie = htole16(cookie); 6446 break; 6447 case BWN_FW_HDR_410: 6448 txhdr->body.r410.cookie = htole16(cookie); 6449 break; 6450 case BWN_FW_HDR_598: 6451 txhdr->body.r598.cookie = htole16(cookie); 6452 break; 6453 } 6454 6455 txhdr->macctl = htole32(macctl); 6456 txhdr->phyctl = htole16(phyctl); 6457 6458 /* 6459 * TX radio tap 6460 */ 6461 if (ieee80211_radiotap_active_vap(vap)) { 6462 sc->sc_tx_th.wt_flags = 0; 6463 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 6464 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 6465 if (isshort && 6466 (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB || 6467 rate == BWN_CCK_RATE_11MB)) 6468 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6469 sc->sc_tx_th.wt_rate = rate; 6470 6471 ieee80211_radiotap_tx(vap, m); 6472 } 6473 6474 return (0); 6475} 6476 6477static void 6478bwn_plcp_genhdr(struct bwn_plcp4 *plcp, const uint16_t octets, 6479 const uint8_t rate) 6480{ 6481 uint32_t d, plen; 6482 uint8_t *raw = plcp->o.raw; 6483 6484 if (BWN_ISOFDMRATE(rate)) { 6485 d = bwn_plcp_getofdm(rate); 6486 KASSERT(!(octets & 0xf000), 6487 ("%s:%d: fail", __func__, __LINE__)); 6488 d |= (octets << 5); 6489 plcp->o.data = htole32(d); 6490 } else { 6491 plen = octets * 16 / rate; 6492 if ((octets * 16 % rate) > 0) { 6493 plen++; 6494 if ((rate == BWN_CCK_RATE_11MB) 6495 && ((octets * 8 % 11) < 4)) { 6496 raw[1] = 0x84; 6497 } else 6498 raw[1] = 0x04; 6499 } else 6500 raw[1] = 0x04; 6501 plcp->o.data |= htole32(plen << 16); 6502 raw[0] = bwn_plcp_getcck(rate); 6503 } 6504} 6505 6506static uint8_t 6507bwn_antenna_sanitize(struct bwn_mac *mac, uint8_t n) 6508{ 6509 struct bwn_softc *sc = mac->mac_sc; 6510 uint8_t mask; 6511 6512 if (n == 0) 6513 return (0); 6514 if (mac->mac_phy.gmode) 6515 mask = siba_sprom_get_ant_bg(sc->sc_dev); 6516 else 6517 mask = siba_sprom_get_ant_a(sc->sc_dev); 6518 if (!(mask & (1 << (n - 1)))) 6519 return (0); 6520 return (n); 6521} 6522 6523/* 6524 * Return a fallback rate for the given rate. 6525 * 6526 * Note: Don't fall back from OFDM to CCK. 6527 */ 6528static uint8_t 6529bwn_get_fbrate(uint8_t bitrate) 6530{ 6531 switch (bitrate) { 6532 /* CCK */ 6533 case BWN_CCK_RATE_1MB: 6534 return (BWN_CCK_RATE_1MB); 6535 case BWN_CCK_RATE_2MB: 6536 return (BWN_CCK_RATE_1MB); 6537 case BWN_CCK_RATE_5MB: 6538 return (BWN_CCK_RATE_2MB); 6539 case BWN_CCK_RATE_11MB: 6540 return (BWN_CCK_RATE_5MB); 6541 6542 /* OFDM */ 6543 case BWN_OFDM_RATE_6MB: 6544 return (BWN_OFDM_RATE_6MB); 6545 case BWN_OFDM_RATE_9MB: 6546 return (BWN_OFDM_RATE_6MB); 6547 case BWN_OFDM_RATE_12MB: 6548 return (BWN_OFDM_RATE_9MB); 6549 case BWN_OFDM_RATE_18MB: 6550 return (BWN_OFDM_RATE_12MB); 6551 case BWN_OFDM_RATE_24MB: 6552 return (BWN_OFDM_RATE_18MB); 6553 case BWN_OFDM_RATE_36MB: 6554 return (BWN_OFDM_RATE_24MB); 6555 case BWN_OFDM_RATE_48MB: 6556 return (BWN_OFDM_RATE_36MB); 6557 case BWN_OFDM_RATE_54MB: 6558 return (BWN_OFDM_RATE_48MB); 6559 } 6560 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 6561 return (0); 6562} 6563 6564static uint32_t 6565bwn_pio_write_multi_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 6566 uint32_t ctl, const void *_data, int len) 6567{ 6568 struct bwn_softc *sc = mac->mac_sc; 6569 uint32_t value = 0; 6570 const uint8_t *data = _data; 6571 6572 ctl |= BWN_PIO8_TXCTL_0_7 | BWN_PIO8_TXCTL_8_15 | 6573 BWN_PIO8_TXCTL_16_23 | BWN_PIO8_TXCTL_24_31; 6574 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl); 6575 6576 siba_write_multi_4(sc->sc_dev, data, (len & ~3), 6577 tq->tq_base + BWN_PIO8_TXDATA); 6578 if (len & 3) { 6579 ctl &= ~(BWN_PIO8_TXCTL_8_15 | BWN_PIO8_TXCTL_16_23 | 6580 BWN_PIO8_TXCTL_24_31); 6581 data = &(data[len - 1]); 6582 switch (len & 3) { 6583 case 3: 6584 ctl |= BWN_PIO8_TXCTL_16_23; 6585 value |= (uint32_t)(*data) << 16; 6586 data--; 6587 case 2: 6588 ctl |= BWN_PIO8_TXCTL_8_15; 6589 value |= (uint32_t)(*data) << 8; 6590 data--; 6591 case 1: 6592 value |= (uint32_t)(*data); 6593 } 6594 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl); 6595 bwn_pio_write_4(mac, tq, BWN_PIO8_TXDATA, value); 6596 } 6597 6598 return (ctl); 6599} 6600 6601static void 6602bwn_pio_write_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 6603 uint16_t offset, uint32_t value) 6604{ 6605 6606 BWN_WRITE_4(mac, tq->tq_base + offset, value); 6607} 6608 6609static uint16_t 6610bwn_pio_write_multi_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 6611 uint16_t ctl, const void *_data, int len) 6612{ 6613 struct bwn_softc *sc = mac->mac_sc; 6614 const uint8_t *data = _data; 6615 6616 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI; 6617 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 6618 6619 siba_write_multi_2(sc->sc_dev, data, (len & ~1), 6620 tq->tq_base + BWN_PIO_TXDATA); 6621 if (len & 1) { 6622 ctl &= ~BWN_PIO_TXCTL_WRITEHI; 6623 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 6624 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data[len - 1]); 6625 } 6626 6627 return (ctl); 6628} 6629 6630static uint16_t 6631bwn_pio_write_mbuf_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 6632 uint16_t ctl, struct mbuf *m0) 6633{ 6634 int i, j = 0; 6635 uint16_t data = 0; 6636 const uint8_t *buf; 6637 struct mbuf *m = m0; 6638 6639 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI; 6640 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 6641 6642 for (; m != NULL; m = m->m_next) { 6643 buf = mtod(m, const uint8_t *); 6644 for (i = 0; i < m->m_len; i++) { 6645 if (!((j++) % 2)) 6646 data |= buf[i]; 6647 else { 6648 data |= (buf[i] << 8); 6649 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data); 6650 data = 0; 6651 } 6652 } 6653 } 6654 if (m0->m_pkthdr.len % 2) { 6655 ctl &= ~BWN_PIO_TXCTL_WRITEHI; 6656 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 6657 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data); 6658 } 6659 6660 return (ctl); 6661} 6662 6663static void 6664bwn_set_slot_time(struct bwn_mac *mac, uint16_t time) 6665{ 6666 6667 /* XXX should exit if 5GHz band .. */ 6668 if (mac->mac_phy.type != BWN_PHYTYPE_G) 6669 return; 6670 6671 BWN_WRITE_2(mac, 0x684, 510 + time); 6672 /* Disabled in Linux b43, can adversely effect performance */ 6673#if 0 6674 bwn_shm_write_2(mac, BWN_SHARED, 0x0010, time); 6675#endif 6676} 6677 6678static struct bwn_dma_ring * 6679bwn_dma_select(struct bwn_mac *mac, uint8_t prio) 6680{ 6681 6682 if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0) 6683 return (mac->mac_method.dma.wme[WME_AC_BE]); 6684 6685 switch (prio) { 6686 case 3: 6687 return (mac->mac_method.dma.wme[WME_AC_VO]); 6688 case 2: 6689 return (mac->mac_method.dma.wme[WME_AC_VI]); 6690 case 0: 6691 return (mac->mac_method.dma.wme[WME_AC_BE]); 6692 case 1: 6693 return (mac->mac_method.dma.wme[WME_AC_BK]); 6694 } 6695 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 6696 return (NULL); 6697} 6698 6699static int 6700bwn_dma_getslot(struct bwn_dma_ring *dr) 6701{ 6702 int slot; 6703 6704 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc); 6705 6706 KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__)); 6707 KASSERT(!(dr->dr_stop), ("%s:%d: fail", __func__, __LINE__)); 6708 KASSERT(bwn_dma_freeslot(dr) != 0, ("%s:%d: fail", __func__, __LINE__)); 6709 6710 slot = bwn_dma_nextslot(dr, dr->dr_curslot); 6711 KASSERT(!(slot & ~0x0fff), ("%s:%d: fail", __func__, __LINE__)); 6712 dr->dr_curslot = slot; 6713 dr->dr_usedslot++; 6714 6715 return (slot); 6716} 6717 6718static struct bwn_pio_txqueue * 6719bwn_pio_parse_cookie(struct bwn_mac *mac, uint16_t cookie, 6720 struct bwn_pio_txpkt **pack) 6721{ 6722 struct bwn_pio *pio = &mac->mac_method.pio; 6723 struct bwn_pio_txqueue *tq = NULL; 6724 unsigned int index; 6725 6726 switch (cookie & 0xf000) { 6727 case 0x1000: 6728 tq = &pio->wme[WME_AC_BK]; 6729 break; 6730 case 0x2000: 6731 tq = &pio->wme[WME_AC_BE]; 6732 break; 6733 case 0x3000: 6734 tq = &pio->wme[WME_AC_VI]; 6735 break; 6736 case 0x4000: 6737 tq = &pio->wme[WME_AC_VO]; 6738 break; 6739 case 0x5000: 6740 tq = &pio->mcast; 6741 break; 6742 } 6743 KASSERT(tq != NULL, ("%s:%d: fail", __func__, __LINE__)); 6744 if (tq == NULL) 6745 return (NULL); 6746 index = (cookie & 0x0fff); 6747 KASSERT(index < N(tq->tq_pkts), ("%s:%d: fail", __func__, __LINE__)); 6748 if (index >= N(tq->tq_pkts)) 6749 return (NULL); 6750 *pack = &tq->tq_pkts[index]; 6751 KASSERT(*pack != NULL, ("%s:%d: fail", __func__, __LINE__)); 6752 return (tq); 6753} 6754 6755static void 6756bwn_txpwr(void *arg, int npending) 6757{ 6758 struct bwn_mac *mac = arg; 6759 struct bwn_softc *sc = mac->mac_sc; 6760 6761 BWN_LOCK(sc); 6762 if (mac && mac->mac_status >= BWN_MAC_STATUS_STARTED && 6763 mac->mac_phy.set_txpwr != NULL) 6764 mac->mac_phy.set_txpwr(mac); 6765 BWN_UNLOCK(sc); 6766} 6767 6768static void 6769bwn_task_15s(struct bwn_mac *mac) 6770{ 6771 uint16_t reg; 6772 6773 if (mac->mac_fw.opensource) { 6774 reg = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG); 6775 if (reg) { 6776 bwn_restart(mac, "fw watchdog"); 6777 return; 6778 } 6779 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG, 1); 6780 } 6781 if (mac->mac_phy.task_15s) 6782 mac->mac_phy.task_15s(mac); 6783 6784 mac->mac_phy.txerrors = BWN_TXERROR_MAX; 6785} 6786 6787static void 6788bwn_task_30s(struct bwn_mac *mac) 6789{ 6790 6791 if (mac->mac_phy.type != BWN_PHYTYPE_G || mac->mac_noise.noi_running) 6792 return; 6793 mac->mac_noise.noi_running = 1; 6794 mac->mac_noise.noi_nsamples = 0; 6795 6796 bwn_noise_gensample(mac); 6797} 6798 6799static void 6800bwn_task_60s(struct bwn_mac *mac) 6801{ 6802 6803 if (mac->mac_phy.task_60s) 6804 mac->mac_phy.task_60s(mac); 6805 bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME); 6806} 6807 6808static void 6809bwn_tasks(void *arg) 6810{ 6811 struct bwn_mac *mac = arg; 6812 struct bwn_softc *sc = mac->mac_sc; 6813 6814 BWN_ASSERT_LOCKED(sc); 6815 if (mac->mac_status != BWN_MAC_STATUS_STARTED) 6816 return; 6817 6818 if (mac->mac_task_state % 4 == 0) 6819 bwn_task_60s(mac); 6820 if (mac->mac_task_state % 2 == 0) 6821 bwn_task_30s(mac); 6822 bwn_task_15s(mac); 6823 6824 mac->mac_task_state++; 6825 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac); 6826} 6827 6828static int 6829bwn_plcp_get_ofdmrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp, uint8_t a) 6830{ 6831 struct bwn_softc *sc = mac->mac_sc; 6832 6833 KASSERT(a == 0, ("not support APHY\n")); 6834 6835 switch (plcp->o.raw[0] & 0xf) { 6836 case 0xb: 6837 return (BWN_OFDM_RATE_6MB); 6838 case 0xf: 6839 return (BWN_OFDM_RATE_9MB); 6840 case 0xa: 6841 return (BWN_OFDM_RATE_12MB); 6842 case 0xe: 6843 return (BWN_OFDM_RATE_18MB); 6844 case 0x9: 6845 return (BWN_OFDM_RATE_24MB); 6846 case 0xd: 6847 return (BWN_OFDM_RATE_36MB); 6848 case 0x8: 6849 return (BWN_OFDM_RATE_48MB); 6850 case 0xc: 6851 return (BWN_OFDM_RATE_54MB); 6852 } 6853 device_printf(sc->sc_dev, "incorrect OFDM rate %d\n", 6854 plcp->o.raw[0] & 0xf); 6855 return (-1); 6856} 6857 6858static int 6859bwn_plcp_get_cckrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp) 6860{ 6861 struct bwn_softc *sc = mac->mac_sc; 6862 6863 switch (plcp->o.raw[0]) { 6864 case 0x0a: 6865 return (BWN_CCK_RATE_1MB); 6866 case 0x14: 6867 return (BWN_CCK_RATE_2MB); 6868 case 0x37: 6869 return (BWN_CCK_RATE_5MB); 6870 case 0x6e: 6871 return (BWN_CCK_RATE_11MB); 6872 } 6873 device_printf(sc->sc_dev, "incorrect CCK rate %d\n", plcp->o.raw[0]); 6874 return (-1); 6875} 6876 6877static void 6878bwn_rx_radiotap(struct bwn_mac *mac, struct mbuf *m, 6879 const struct bwn_rxhdr4 *rxhdr, struct bwn_plcp6 *plcp, int rate, 6880 int rssi, int noise) 6881{ 6882 struct bwn_softc *sc = mac->mac_sc; 6883 const struct ieee80211_frame_min *wh; 6884 uint64_t tsf; 6885 uint16_t low_mactime_now; 6886 uint16_t mt; 6887 6888 if (htole16(rxhdr->phy_status0) & BWN_RX_PHYST0_SHORTPRMBL) 6889 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6890 6891 wh = mtod(m, const struct ieee80211_frame_min *); 6892 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 6893 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 6894 6895 bwn_tsf_read(mac, &tsf); 6896 low_mactime_now = tsf; 6897 tsf = tsf & ~0xffffULL; 6898 6899 switch (mac->mac_fw.fw_hdr_format) { 6900 case BWN_FW_HDR_351: 6901 case BWN_FW_HDR_410: 6902 mt = le16toh(rxhdr->ps4.r351.mac_time); 6903 break; 6904 case BWN_FW_HDR_598: 6905 mt = le16toh(rxhdr->ps4.r598.mac_time); 6906 break; 6907 } 6908 6909 tsf += mt; 6910 if (low_mactime_now < mt) 6911 tsf -= 0x10000; 6912 6913 sc->sc_rx_th.wr_tsf = tsf; 6914 sc->sc_rx_th.wr_rate = rate; 6915 sc->sc_rx_th.wr_antsignal = rssi; 6916 sc->sc_rx_th.wr_antnoise = noise; 6917} 6918 6919static void 6920bwn_tsf_read(struct bwn_mac *mac, uint64_t *tsf) 6921{ 6922 uint32_t low, high; 6923 6924 KASSERT(siba_get_revid(mac->mac_sc->sc_dev) >= 3, 6925 ("%s:%d: fail", __func__, __LINE__)); 6926 6927 low = BWN_READ_4(mac, BWN_REV3PLUS_TSF_LOW); 6928 high = BWN_READ_4(mac, BWN_REV3PLUS_TSF_HIGH); 6929 *tsf = high; 6930 *tsf <<= 32; 6931 *tsf |= low; 6932} 6933 6934static int 6935bwn_dma_attach(struct bwn_mac *mac) 6936{ 6937 struct bwn_dma *dma = &mac->mac_method.dma; 6938 struct bwn_softc *sc = mac->mac_sc; 6939 bus_addr_t lowaddr = 0; 6940 int error; 6941 6942 if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0) 6943 return (0); 6944 6945 KASSERT(siba_get_revid(sc->sc_dev) >= 5, ("%s: fail", __func__)); 6946 6947 mac->mac_flags |= BWN_MAC_FLAG_DMA; 6948 6949 dma->dmatype = bwn_dma_gettype(mac); 6950 if (dma->dmatype == BWN_DMA_30BIT) 6951 lowaddr = BWN_BUS_SPACE_MAXADDR_30BIT; 6952 else if (dma->dmatype == BWN_DMA_32BIT) 6953 lowaddr = BUS_SPACE_MAXADDR_32BIT; 6954 else 6955 lowaddr = BUS_SPACE_MAXADDR; 6956 6957 /* 6958 * Create top level DMA tag 6959 */ 6960 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 6961 BWN_ALIGN, 0, /* alignment, bounds */ 6962 lowaddr, /* lowaddr */ 6963 BUS_SPACE_MAXADDR, /* highaddr */ 6964 NULL, NULL, /* filter, filterarg */ 6965 BUS_SPACE_MAXSIZE, /* maxsize */ 6966 BUS_SPACE_UNRESTRICTED, /* nsegments */ 6967 BUS_SPACE_MAXSIZE, /* maxsegsize */ 6968 0, /* flags */ 6969 NULL, NULL, /* lockfunc, lockarg */ 6970 &dma->parent_dtag); 6971 if (error) { 6972 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 6973 return (error); 6974 } 6975 6976 /* 6977 * Create TX/RX mbuf DMA tag 6978 */ 6979 error = bus_dma_tag_create(dma->parent_dtag, 6980 1, 6981 0, 6982 BUS_SPACE_MAXADDR, 6983 BUS_SPACE_MAXADDR, 6984 NULL, NULL, 6985 MCLBYTES, 6986 1, 6987 BUS_SPACE_MAXSIZE_32BIT, 6988 0, 6989 NULL, NULL, 6990 &dma->rxbuf_dtag); 6991 if (error) { 6992 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 6993 goto fail0; 6994 } 6995 error = bus_dma_tag_create(dma->parent_dtag, 6996 1, 6997 0, 6998 BUS_SPACE_MAXADDR, 6999 BUS_SPACE_MAXADDR, 7000 NULL, NULL, 7001 MCLBYTES, 7002 1, 7003 BUS_SPACE_MAXSIZE_32BIT, 7004 0, 7005 NULL, NULL, 7006 &dma->txbuf_dtag); 7007 if (error) { 7008 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 7009 goto fail1; 7010 } 7011 7012 dma->wme[WME_AC_BK] = bwn_dma_ringsetup(mac, 0, 1, dma->dmatype); 7013 if (!dma->wme[WME_AC_BK]) 7014 goto fail2; 7015 7016 dma->wme[WME_AC_BE] = bwn_dma_ringsetup(mac, 1, 1, dma->dmatype); 7017 if (!dma->wme[WME_AC_BE]) 7018 goto fail3; 7019 7020 dma->wme[WME_AC_VI] = bwn_dma_ringsetup(mac, 2, 1, dma->dmatype); 7021 if (!dma->wme[WME_AC_VI]) 7022 goto fail4; 7023 7024 dma->wme[WME_AC_VO] = bwn_dma_ringsetup(mac, 3, 1, dma->dmatype); 7025 if (!dma->wme[WME_AC_VO]) 7026 goto fail5; 7027 7028 dma->mcast = bwn_dma_ringsetup(mac, 4, 1, dma->dmatype); 7029 if (!dma->mcast) 7030 goto fail6; 7031 dma->rx = bwn_dma_ringsetup(mac, 0, 0, dma->dmatype); 7032 if (!dma->rx) 7033 goto fail7; 7034 7035 return (error); 7036 7037fail7: bwn_dma_ringfree(&dma->mcast); 7038fail6: bwn_dma_ringfree(&dma->wme[WME_AC_VO]); 7039fail5: bwn_dma_ringfree(&dma->wme[WME_AC_VI]); 7040fail4: bwn_dma_ringfree(&dma->wme[WME_AC_BE]); 7041fail3: bwn_dma_ringfree(&dma->wme[WME_AC_BK]); 7042fail2: bus_dma_tag_destroy(dma->txbuf_dtag); 7043fail1: bus_dma_tag_destroy(dma->rxbuf_dtag); 7044fail0: bus_dma_tag_destroy(dma->parent_dtag); 7045 return (error); 7046} 7047 7048static struct bwn_dma_ring * 7049bwn_dma_parse_cookie(struct bwn_mac *mac, const struct bwn_txstatus *status, 7050 uint16_t cookie, int *slot) 7051{ 7052 struct bwn_dma *dma = &mac->mac_method.dma; 7053 struct bwn_dma_ring *dr; 7054 struct bwn_softc *sc = mac->mac_sc; 7055 7056 BWN_ASSERT_LOCKED(mac->mac_sc); 7057 7058 switch (cookie & 0xf000) { 7059 case 0x1000: 7060 dr = dma->wme[WME_AC_BK]; 7061 break; 7062 case 0x2000: 7063 dr = dma->wme[WME_AC_BE]; 7064 break; 7065 case 0x3000: 7066 dr = dma->wme[WME_AC_VI]; 7067 break; 7068 case 0x4000: 7069 dr = dma->wme[WME_AC_VO]; 7070 break; 7071 case 0x5000: 7072 dr = dma->mcast; 7073 break; 7074 default: 7075 dr = NULL; 7076 KASSERT(0 == 1, 7077 ("invalid cookie value %d", cookie & 0xf000)); 7078 } 7079 *slot = (cookie & 0x0fff); 7080 if (*slot < 0 || *slot >= dr->dr_numslots) { 7081 /* 7082 * XXX FIXME: sometimes H/W returns TX DONE events duplicately 7083 * that it occurs events which have same H/W sequence numbers. 7084 * When it's occurred just prints a WARNING msgs and ignores. 7085 */ 7086 KASSERT(status->seq == dma->lastseq, 7087 ("%s:%d: fail", __func__, __LINE__)); 7088 device_printf(sc->sc_dev, 7089 "out of slot ranges (0 < %d < %d)\n", *slot, 7090 dr->dr_numslots); 7091 return (NULL); 7092 } 7093 dma->lastseq = status->seq; 7094 return (dr); 7095} 7096 7097static void 7098bwn_dma_stop(struct bwn_mac *mac) 7099{ 7100 struct bwn_dma *dma; 7101 7102 if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0) 7103 return; 7104 dma = &mac->mac_method.dma; 7105 7106 bwn_dma_ringstop(&dma->rx); 7107 bwn_dma_ringstop(&dma->wme[WME_AC_BK]); 7108 bwn_dma_ringstop(&dma->wme[WME_AC_BE]); 7109 bwn_dma_ringstop(&dma->wme[WME_AC_VI]); 7110 bwn_dma_ringstop(&dma->wme[WME_AC_VO]); 7111 bwn_dma_ringstop(&dma->mcast); 7112} 7113 7114static void 7115bwn_dma_ringstop(struct bwn_dma_ring **dr) 7116{ 7117 7118 if (dr == NULL) 7119 return; 7120 7121 bwn_dma_cleanup(*dr); 7122} 7123 7124static void 7125bwn_pio_stop(struct bwn_mac *mac) 7126{ 7127 struct bwn_pio *pio; 7128 7129 if (mac->mac_flags & BWN_MAC_FLAG_DMA) 7130 return; 7131 pio = &mac->mac_method.pio; 7132 7133 bwn_destroy_queue_tx(&pio->mcast); 7134 bwn_destroy_queue_tx(&pio->wme[WME_AC_VO]); 7135 bwn_destroy_queue_tx(&pio->wme[WME_AC_VI]); 7136 bwn_destroy_queue_tx(&pio->wme[WME_AC_BE]); 7137 bwn_destroy_queue_tx(&pio->wme[WME_AC_BK]); 7138} 7139 7140static void 7141bwn_led_attach(struct bwn_mac *mac) 7142{ 7143 struct bwn_softc *sc = mac->mac_sc; 7144 const uint8_t *led_act = NULL; 7145 uint16_t val[BWN_LED_MAX]; 7146 int i; 7147 7148 sc->sc_led_idle = (2350 * hz) / 1000; 7149 sc->sc_led_blink = 1; 7150 7151 for (i = 0; i < N(bwn_vendor_led_act); ++i) { 7152 if (siba_get_pci_subvendor(sc->sc_dev) == 7153 bwn_vendor_led_act[i].vid) { 7154 led_act = bwn_vendor_led_act[i].led_act; 7155 break; 7156 } 7157 } 7158 if (led_act == NULL) 7159 led_act = bwn_default_led_act; 7160 7161 val[0] = siba_sprom_get_gpio0(sc->sc_dev); 7162 val[1] = siba_sprom_get_gpio1(sc->sc_dev); 7163 val[2] = siba_sprom_get_gpio2(sc->sc_dev); 7164 val[3] = siba_sprom_get_gpio3(sc->sc_dev); 7165 7166 for (i = 0; i < BWN_LED_MAX; ++i) { 7167 struct bwn_led *led = &sc->sc_leds[i]; 7168 7169 if (val[i] == 0xff) { 7170 led->led_act = led_act[i]; 7171 } else { 7172 if (val[i] & BWN_LED_ACT_LOW) 7173 led->led_flags |= BWN_LED_F_ACTLOW; 7174 led->led_act = val[i] & BWN_LED_ACT_MASK; 7175 } 7176 led->led_mask = (1 << i); 7177 7178 if (led->led_act == BWN_LED_ACT_BLINK_SLOW || 7179 led->led_act == BWN_LED_ACT_BLINK_POLL || 7180 led->led_act == BWN_LED_ACT_BLINK) { 7181 led->led_flags |= BWN_LED_F_BLINK; 7182 if (led->led_act == BWN_LED_ACT_BLINK_POLL) 7183 led->led_flags |= BWN_LED_F_POLLABLE; 7184 else if (led->led_act == BWN_LED_ACT_BLINK_SLOW) 7185 led->led_flags |= BWN_LED_F_SLOW; 7186 7187 if (sc->sc_blink_led == NULL) { 7188 sc->sc_blink_led = led; 7189 if (led->led_flags & BWN_LED_F_SLOW) 7190 BWN_LED_SLOWDOWN(sc->sc_led_idle); 7191 } 7192 } 7193 7194 DPRINTF(sc, BWN_DEBUG_LED, 7195 "%dth led, act %d, lowact %d\n", i, 7196 led->led_act, led->led_flags & BWN_LED_F_ACTLOW); 7197 } 7198 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 7199} 7200 7201static __inline uint16_t 7202bwn_led_onoff(const struct bwn_led *led, uint16_t val, int on) 7203{ 7204 7205 if (led->led_flags & BWN_LED_F_ACTLOW) 7206 on = !on; 7207 if (on) 7208 val |= led->led_mask; 7209 else 7210 val &= ~led->led_mask; 7211 return val; 7212} 7213 7214static void 7215bwn_led_newstate(struct bwn_mac *mac, enum ieee80211_state nstate) 7216{ 7217 struct bwn_softc *sc = mac->mac_sc; 7218 struct ieee80211com *ic = &sc->sc_ic; 7219 uint16_t val; 7220 int i; 7221 7222 if (nstate == IEEE80211_S_INIT) { 7223 callout_stop(&sc->sc_led_blink_ch); 7224 sc->sc_led_blinking = 0; 7225 } 7226 7227 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) 7228 return; 7229 7230 val = BWN_READ_2(mac, BWN_GPIO_CONTROL); 7231 for (i = 0; i < BWN_LED_MAX; ++i) { 7232 struct bwn_led *led = &sc->sc_leds[i]; 7233 int on; 7234 7235 if (led->led_act == BWN_LED_ACT_UNKN || 7236 led->led_act == BWN_LED_ACT_NULL) 7237 continue; 7238 7239 if ((led->led_flags & BWN_LED_F_BLINK) && 7240 nstate != IEEE80211_S_INIT) 7241 continue; 7242 7243 switch (led->led_act) { 7244 case BWN_LED_ACT_ON: /* Always on */ 7245 on = 1; 7246 break; 7247 case BWN_LED_ACT_OFF: /* Always off */ 7248 case BWN_LED_ACT_5GHZ: /* TODO: 11A */ 7249 on = 0; 7250 break; 7251 default: 7252 on = 1; 7253 switch (nstate) { 7254 case IEEE80211_S_INIT: 7255 on = 0; 7256 break; 7257 case IEEE80211_S_RUN: 7258 if (led->led_act == BWN_LED_ACT_11G && 7259 ic->ic_curmode != IEEE80211_MODE_11G) 7260 on = 0; 7261 break; 7262 default: 7263 if (led->led_act == BWN_LED_ACT_ASSOC) 7264 on = 0; 7265 break; 7266 } 7267 break; 7268 } 7269 7270 val = bwn_led_onoff(led, val, on); 7271 } 7272 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val); 7273} 7274 7275static void 7276bwn_led_event(struct bwn_mac *mac, int event) 7277{ 7278 struct bwn_softc *sc = mac->mac_sc; 7279 struct bwn_led *led = sc->sc_blink_led; 7280 int rate; 7281 7282 if (event == BWN_LED_EVENT_POLL) { 7283 if ((led->led_flags & BWN_LED_F_POLLABLE) == 0) 7284 return; 7285 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 7286 return; 7287 } 7288 7289 sc->sc_led_ticks = ticks; 7290 if (sc->sc_led_blinking) 7291 return; 7292 7293 switch (event) { 7294 case BWN_LED_EVENT_RX: 7295 rate = sc->sc_rx_rate; 7296 break; 7297 case BWN_LED_EVENT_TX: 7298 rate = sc->sc_tx_rate; 7299 break; 7300 case BWN_LED_EVENT_POLL: 7301 rate = 0; 7302 break; 7303 default: 7304 panic("unknown LED event %d\n", event); 7305 break; 7306 } 7307 bwn_led_blink_start(mac, bwn_led_duration[rate].on_dur, 7308 bwn_led_duration[rate].off_dur); 7309} 7310 7311static void 7312bwn_led_blink_start(struct bwn_mac *mac, int on_dur, int off_dur) 7313{ 7314 struct bwn_softc *sc = mac->mac_sc; 7315 struct bwn_led *led = sc->sc_blink_led; 7316 uint16_t val; 7317 7318 val = BWN_READ_2(mac, BWN_GPIO_CONTROL); 7319 val = bwn_led_onoff(led, val, 1); 7320 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val); 7321 7322 if (led->led_flags & BWN_LED_F_SLOW) { 7323 BWN_LED_SLOWDOWN(on_dur); 7324 BWN_LED_SLOWDOWN(off_dur); 7325 } 7326 7327 sc->sc_led_blinking = 1; 7328 sc->sc_led_blink_offdur = off_dur; 7329 7330 callout_reset(&sc->sc_led_blink_ch, on_dur, bwn_led_blink_next, mac); 7331} 7332 7333static void 7334bwn_led_blink_next(void *arg) 7335{ 7336 struct bwn_mac *mac = arg; 7337 struct bwn_softc *sc = mac->mac_sc; 7338 uint16_t val; 7339 7340 val = BWN_READ_2(mac, BWN_GPIO_CONTROL); 7341 val = bwn_led_onoff(sc->sc_blink_led, val, 0); 7342 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val); 7343 7344 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 7345 bwn_led_blink_end, mac); 7346} 7347 7348static void 7349bwn_led_blink_end(void *arg) 7350{ 7351 struct bwn_mac *mac = arg; 7352 struct bwn_softc *sc = mac->mac_sc; 7353 7354 sc->sc_led_blinking = 0; 7355} 7356 7357static int 7358bwn_suspend(device_t dev) 7359{ 7360 struct bwn_softc *sc = device_get_softc(dev); 7361 7362 BWN_LOCK(sc); 7363 bwn_stop(sc); 7364 BWN_UNLOCK(sc); 7365 return (0); 7366} 7367 7368static int 7369bwn_resume(device_t dev) 7370{ 7371 struct bwn_softc *sc = device_get_softc(dev); 7372 int error = EDOOFUS; 7373 7374 BWN_LOCK(sc); 7375 if (sc->sc_ic.ic_nrunning > 0) 7376 error = bwn_init(sc); 7377 BWN_UNLOCK(sc); 7378 if (error == 0) 7379 ieee80211_start_all(&sc->sc_ic); 7380 return (0); 7381} 7382 7383static void 7384bwn_rfswitch(void *arg) 7385{ 7386 struct bwn_softc *sc = arg; 7387 struct bwn_mac *mac = sc->sc_curmac; 7388 int cur = 0, prev = 0; 7389 7390 KASSERT(mac->mac_status >= BWN_MAC_STATUS_STARTED, 7391 ("%s: invalid MAC status %d", __func__, mac->mac_status)); 7392 7393 if (mac->mac_phy.rev >= 3 || mac->mac_phy.type == BWN_PHYTYPE_LP 7394 || mac->mac_phy.type == BWN_PHYTYPE_N) { 7395 if (!(BWN_READ_4(mac, BWN_RF_HWENABLED_HI) 7396 & BWN_RF_HWENABLED_HI_MASK)) 7397 cur = 1; 7398 } else { 7399 if (BWN_READ_2(mac, BWN_RF_HWENABLED_LO) 7400 & BWN_RF_HWENABLED_LO_MASK) 7401 cur = 1; 7402 } 7403 7404 if (mac->mac_flags & BWN_MAC_FLAG_RADIO_ON) 7405 prev = 1; 7406 7407 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called; cur=%d, prev=%d\n", 7408 __func__, cur, prev); 7409 7410 if (cur != prev) { 7411 if (cur) 7412 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON; 7413 else 7414 mac->mac_flags &= ~BWN_MAC_FLAG_RADIO_ON; 7415 7416 device_printf(sc->sc_dev, 7417 "status of RF switch is changed to %s\n", 7418 cur ? "ON" : "OFF"); 7419 if (cur != mac->mac_phy.rf_on) { 7420 if (cur) 7421 bwn_rf_turnon(mac); 7422 else 7423 bwn_rf_turnoff(mac); 7424 } 7425 } 7426 7427 callout_schedule(&sc->sc_rfswitch_ch, hz); 7428} 7429 7430static void 7431bwn_sysctl_node(struct bwn_softc *sc) 7432{ 7433 device_t dev = sc->sc_dev; 7434 struct bwn_mac *mac; 7435 struct bwn_stats *stats; 7436 7437 /* XXX assume that count of MAC is only 1. */ 7438 7439 if ((mac = sc->sc_curmac) == NULL) 7440 return; 7441 stats = &mac->mac_stats; 7442 7443 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 7444 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 7445 "linknoise", CTLFLAG_RW, &stats->rts, 0, "Noise level"); 7446 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 7447 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 7448 "rts", CTLFLAG_RW, &stats->rts, 0, "RTS"); 7449 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 7450 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 7451 "rtsfail", CTLFLAG_RW, &stats->rtsfail, 0, "RTS failed to send"); 7452 7453#ifdef BWN_DEBUG 7454 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 7455 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 7456 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 7457#endif 7458} 7459 7460static device_method_t bwn_methods[] = { 7461 /* Device interface */ 7462 DEVMETHOD(device_probe, bwn_probe), 7463 DEVMETHOD(device_attach, bwn_attach), 7464 DEVMETHOD(device_detach, bwn_detach), 7465 DEVMETHOD(device_suspend, bwn_suspend), 7466 DEVMETHOD(device_resume, bwn_resume), 7467 DEVMETHOD_END 7468}; 7469static driver_t bwn_driver = { 7470 "bwn", 7471 bwn_methods, 7472 sizeof(struct bwn_softc) 7473}; 7474static devclass_t bwn_devclass; 7475DRIVER_MODULE(bwn, siba_bwn, bwn_driver, bwn_devclass, 0, 0); 7476MODULE_DEPEND(bwn, siba_bwn, 1, 1, 1); 7477MODULE_DEPEND(bwn, wlan, 1, 1, 1); /* 802.11 media layer */ 7478MODULE_DEPEND(bwn, firmware, 1, 1, 1); /* firmware support */ 7479MODULE_DEPEND(bwn, wlan_amrr, 1, 1, 1); 7480MODULE_VERSION(bwn, 1); 7481