Searched refs:cw6 (Results 1 - 12 of 12) sorted by last modified time

/linux-master/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn32.c219 const struct dmub_window *cw6,
258 offset = cw6->offset;
262 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
264 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
214 dmub_dcn32_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6) argument
H A Ddmub_dcn35.c232 const struct dmub_window *cw6,
271 offset = cw6->offset;
275 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
277 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
227 dmub_dcn35_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6) argument
H A Ddmub_dcn20.c194 const struct dmub_window *cw6,
264 dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset);
268 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
270 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
189 dmub_dcn20_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6) argument
H A Ddmub_dcn31.c190 const struct dmub_window *cw6,
229 offset = cw6->offset;
233 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
235 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
185 dmub_dcn31_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6) argument
H A Ddmub_srv.c577 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; local
656 cw6.offset.quad_part = fw_state_fb->gpu_addr;
657 cw6.region.base = DMUB_CW6_BASE;
658 cw6.region.top = cw6.region.base + fw_state_fb->size;
671 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, &region6);
H A Ddmub_dcn35.h222 const struct dmub_window *cw6,
H A Ddmub_dcn32.h209 const struct dmub_window *cw6,
H A Ddmub_dcn31.h202 const struct dmub_window *cw6,
H A Ddmub_dcn30.h46 const struct dmub_window *cw6,
H A Ddmub_dcn20.h200 const struct dmub_window *cw6,
H A Ddmub_dcn30.c127 const struct dmub_window *cw6,
194 offset = cw6->offset;
198 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
200 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
122 dmub_dcn30_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6) argument
/linux-master/drivers/gpu/drm/amd/display/dmub/
H A Ddmub_srv.h388 const struct dmub_window *cw6,

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