Searched refs:cw5 (Results 1 - 12 of 12) sorted by last modified time

/linux-master/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn32.c218 const struct dmub_window *cw5,
242 offset = cw5->offset;
246 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
248 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
255 cw5->region.top - cw5->region.base - 1,
214 dmub_dcn32_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6) argument
H A Ddmub_dcn35.c231 const struct dmub_window *cw5,
255 offset = cw5->offset;
259 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
261 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
268 cw5->region.top - cw5->region.base - 1,
227 dmub_dcn35_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6) argument
H A Ddmub_dcn20.c193 const struct dmub_window *cw5,
248 dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset);
252 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
254 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
261 cw5->region.top - cw5->region.base - 1,
189 dmub_dcn20_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6) argument
H A Ddmub_dcn31.c189 const struct dmub_window *cw5,
213 offset = cw5->offset;
217 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
219 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
226 cw5->region.top - cw5->region.base - 1,
185 dmub_dcn31_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6) argument
H A Ddmub_srv.c577 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; local
649 cw5.offset.quad_part = tracebuff_fb->gpu_addr;
650 cw5.region.base = DMUB_CW5_BASE;
651 cw5.region.top = cw5.region.base + tracebuff_fb->size;
671 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, &region6);
H A Ddmub_dcn35.h221 const struct dmub_window *cw5,
H A Ddmub_dcn32.h208 const struct dmub_window *cw5,
H A Ddmub_dcn31.h201 const struct dmub_window *cw5,
H A Ddmub_dcn30.h45 const struct dmub_window *cw5,
H A Ddmub_dcn20.h199 const struct dmub_window *cw5,
H A Ddmub_dcn30.c126 const struct dmub_window *cw5,
178 offset = cw5->offset;
182 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
184 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
191 cw5->region.top - cw5->region.base - 1,
122 dmub_dcn30_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6) argument
/linux-master/drivers/gpu/drm/amd/display/dmub/
H A Ddmub_srv.h387 const struct dmub_window *cw5,

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