Searched refs:cw4 (Results 1 - 12 of 12) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn30.h44 const struct dmub_window *cw4,
H A Ddmub_dcn30.c125 const struct dmub_window *cw4,
159 offset = cw4->offset;
165 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
167 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
174 cw4->region.top - cw4->region.base - 1,
122 dmub_dcn30_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6) argument
H A Ddmub_dcn20.c192 const struct dmub_window *cw4,
229 dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset);
235 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
237 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
244 cw4->region.top - cw4->region.base - 1,
189 dmub_dcn20_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6) argument
H A Ddmub_srv.c577 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; local
633 cw4.offset.quad_part = mail_fb->gpu_addr;
634 cw4.region.base = DMUB_CW4_BASE;
635 cw4.region.top = cw4.region.base + mail_fb->size;
644 inbox1.base = cw4.region.base;
645 inbox1.top = cw4.region.base + DMUB_RB_SIZE;
647 outbox1.top = cw4.region.top;
671 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, &region6);
H A Ddmub_dcn31.c188 const struct dmub_window *cw4,
204 offset = cw4->offset;
208 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
210 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
185 dmub_dcn31_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6) argument
H A Ddmub_dcn32.c217 const struct dmub_window *cw4,
233 offset = cw4->offset;
237 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
239 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
214 dmub_dcn32_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6) argument
H A Ddmub_dcn35.c230 const struct dmub_window *cw4,
246 offset = cw4->offset;
250 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
252 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
227 dmub_dcn35_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6) argument
H A Ddmub_dcn20.h198 const struct dmub_window *cw4,
H A Ddmub_dcn31.h200 const struct dmub_window *cw4,
H A Ddmub_dcn32.h207 const struct dmub_window *cw4,
H A Ddmub_dcn35.h220 const struct dmub_window *cw4,
/linux-master/drivers/gpu/drm/amd/display/dmub/
H A Ddmub_srv.h386 const struct dmub_window *cw4,

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