Searched refs:cw1 (Results 1 - 12 of 12) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn30.h39 const struct dmub_window *cw1);
H A Ddmub_dcn30.c89 const struct dmub_window *cw1)
109 dmub_dcn30_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
113 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
115 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
87 dmub_dcn30_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1) argument
H A Ddmub_dcn32.c153 const struct dmub_window *cw1)
171 dmub_dcn32_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
175 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
177 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
186 const struct dmub_window *cw1)
201 offset = cw1->offset;
205 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
207 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
151 dmub_dcn32_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1) argument
184 dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1) argument
H A Ddmub_dcn35.c174 const struct dmub_window *cw1)
190 dmub_dcn35_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
194 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
196 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
205 const struct dmub_window *cw1)
217 offset = cw1->offset;
220 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
222 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
172 dmub_dcn35_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1) argument
203 dmub_dcn35_backdoor_load_zfb_mode(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1) argument
H A Ddmub_dcn20.c156 const struct dmub_window *cw1)
176 dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
180 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
182 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
154 dmub_dcn20_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1) argument
H A Ddmub_dcn31.c154 const struct dmub_window *cw1)
172 dmub_dcn31_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
176 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
178 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
152 dmub_dcn31_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1) argument
H A Ddmub_dcn32.h198 const struct dmub_window *cw1);
202 const struct dmub_window *cw1);
H A Ddmub_srv.c577 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; local
603 cw1.offset.quad_part = stack_fb->gpu_addr;
604 cw1.region.base = DMUB_CW1_BASE;
605 cw1.region.top = cw1.region.base + stack_fb->size - 1;
620 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1);
622 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
H A Ddmub_dcn35.h211 const struct dmub_window *cw1);
215 const struct dmub_window *cw1);
H A Ddmub_dcn20.h193 const struct dmub_window *cw1);
H A Ddmub_dcn31.h195 const struct dmub_window *cw1);
/linux-master/drivers/gpu/drm/amd/display/dmub/
H A Ddmub_srv.h378 const struct dmub_window *cw1);
382 const struct dmub_window *cw1);

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