| /linux-master/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_dcn30.h | 38 const struct dmub_window *cw0,
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| H A D | dmub_dcn30.c | 88 const struct dmub_window *cw0,
100 dmub_dcn30_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
104 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
106 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
87 dmub_dcn30_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1) argument
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| H A D | dmub_dcn32.c | 152 const struct dmub_window *cw0,
162 dmub_dcn32_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
166 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
168 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
185 const struct dmub_window *cw0,
192 offset = cw0->offset;
196 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
198 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
151 dmub_dcn32_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1) argument
184 dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1) argument
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| H A D | dmub_dcn35.c | 173 const struct dmub_window *cw0,
181 dmub_dcn35_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
185 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
187 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
204 const struct dmub_window *cw0,
210 offset = cw0->offset;
213 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
215 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
172 dmub_dcn35_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1) argument
203 dmub_dcn35_backdoor_load_zfb_mode(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1) argument
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| H A D | dmub_dcn20.c | 155 const struct dmub_window *cw0,
167 dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
171 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
173 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
154 dmub_dcn20_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1) argument
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| H A D | dmub_dcn31.c | 153 const struct dmub_window *cw0,
163 dmub_dcn31_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
167 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
169 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
152 dmub_dcn31_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1) argument
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| H A D | dmub_dcn32.h | 197 const struct dmub_window *cw0,
201 const struct dmub_window *cw0,
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| H A D | dmub_srv.c | 577 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; local
599 cw0.offset.quad_part = inst_fb->gpu_addr;
600 cw0.region.base = DMUB_CW0_BASE;
601 cw0.region.top = cw0.region.base + inst_fb->size - 1;
620 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1);
622 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
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| H A D | dmub_dcn35.h | 210 const struct dmub_window *cw0,
214 const struct dmub_window *cw0,
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| H A D | dmub_dcn20.h | 192 const struct dmub_window *cw0,
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| H A D | dmub_dcn31.h | 194 const struct dmub_window *cw0,
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| /linux-master/drivers/gpu/drm/amd/display/dmub/ |
| H A D | dmub_srv.h | 377 const struct dmub_window *cw0,
381 const struct dmub_window *cw0,
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