| /linux-master/drivers/rtc/ |
| H A D | rtc-xgene.c | 37 void __iomem *csr_base; member in struct:xgene_rtc_dev
47 rtc_time64_to_tm(readl(pdata->csr_base + RTC_CCVR), tm);
59 writel((u32)rtc_tm_to_time64(tm), pdata->csr_base + RTC_CLR);
60 readl(pdata->csr_base + RTC_CLR); /* Force a barrier */
71 alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE;
81 ccr = readl(pdata->csr_base + RTC_CCR);
89 writel(ccr, pdata->csr_base + RTC_CCR);
98 return readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE ? 1 : 0;
105 writel((u32)rtc_tm_to_time64(&alrm->time), pdata->csr_base + RTC_CMR);
125 if (!(readl(pdata->csr_base
[all...] |
| /linux-master/drivers/char/hw_random/ |
| H A D | xgene-rng.c | 80 void __iomem *csr_base; member in struct:xgene_rng_dev
111 writel(fro_val, ctx->csr_base + RNG_FRODETUNE);
112 writel(0x00000000, ctx->csr_base + RNG_ALARMMASK);
113 writel(0x00000000, ctx->csr_base + RNG_ALARMSTOP);
114 writel(0xFFFFFFFF, ctx->csr_base + RNG_FROENABLE);
121 val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
167 frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
192 frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
197 writel(val, ctx->csr_base + RNG_INTR_STS_ACK);
216 val = readl(ctx->csr_base
[all...] |
| /linux-master/drivers/mtd/nand/raw/ |
| H A D | denali_pci.c | 32 resource_size_t csr_base, mem_base; local
51 csr_base = pci_resource_start(dev, 1);
54 csr_base = pci_resource_start(dev, 0);
59 mem_base = csr_base + csr_len;
77 denali->reg = devm_ioremap(denali->dev, csr_base, csr_len);
|
| /linux-master/drivers/pci/controller/ |
| H A D | pcie-altera-msi.c | 34 void __iomem *csr_base; member in struct:altera_msi
44 writel_relaxed(value, msi->csr_base + reg);
49 return readl_relaxed(msi->csr_base + reg);
227 msi->csr_base = devm_platform_ioremap_resource_byname(pdev, "csr");
228 if (IS_ERR(msi->csr_base)) {
230 return PTR_ERR(msi->csr_base);
|
| H A D | pci-xgene.c | 65 void __iomem *csr_base; member in struct:xgene_pcie
74 return readl(port->csr_base + reg);
79 writel(val, port->csr_base + reg);
242 port->csr_base = devm_pci_remap_cfg_resource(dev, &csr);
243 if (IS_ERR(port->csr_base))
244 return PTR_ERR(port->csr_base);
351 port->csr_base = devm_pci_remap_cfg_resource(dev, res);
352 if (IS_ERR(port->csr_base))
353 return PTR_ERR(port->csr_base);
|
| /linux-master/drivers/net/mdio/ |
| H A D | mdio-xgene.c | 332 void __iomem *csr_base; local
345 csr_base = devm_platform_ioremap_resource(pdev, 0);
346 if (IS_ERR(csr_base))
347 return PTR_ERR(csr_base);
348 pdata->mac_csr_addr = csr_base;
349 pdata->mdio_csr_addr = csr_base + BLOCK_XG_MDIO_CSR_OFFSET;
350 pdata->diag_csr_addr = csr_base + BLOCK_DIAG_CSR_OFFSET;
|
| /linux-master/drivers/ata/ |
| H A D | sata_fsl.c | 284 void __iomem *csr_base; member in struct:sata_fsl_host_priv
353 void __iomem *csr_base = host_priv->csr_base; local
356 rx_watermark = ioread32(csr_base + TRANSCFG);
371 void __iomem *csr_base = host_priv->csr_base; local
380 temp = ioread32(csr_base + TRANSCFG);
382 iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
564 ioread32(COMMANDSTAT + host_priv->csr_base));
641 ioread32(host_priv->csr_base
1427 void __iomem *csr_base = NULL; local
[all...] |
| /linux-master/drivers/crypto/intel/qat/qat_common/ |
| H A D | adf_accel_devices.h | 290 #define ADF_CSR_WR(csr_base, csr_offset, val) \
291 __raw_writel(val, csr_base + csr_offset)
294 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset)
|
| /linux-master/drivers/phy/ |
| H A D | phy-xgene.c | 551 static void sds_wr(void __iomem *csr_base, u32 indirect_cmd_reg, argument
560 writel(data, csr_base + indirect_data_reg);
561 readl(csr_base + indirect_data_reg); /* Force a barrier */
562 writel(cmd, csr_base + indirect_cmd_reg);
563 readl(csr_base + indirect_cmd_reg); /* Force a barrier */
565 val = readl(csr_base + indirect_cmd_reg);
570 csr_base + indirect_cmd_reg, addr, data);
573 static void sds_rd(void __iomem *csr_base, u32 indirect_cmd_reg, argument
582 writel(cmd, csr_base + indirect_cmd_reg);
583 readl(csr_base
[all...] |