| /linux-master/arch/arm/mach-omap2/ |
| H A D | cm.h | 60 void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
61 void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs);
62 u32 (*xlate_clkctrl)(u8 part, u16 inst, u16 clkctrl_offs);
71 int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
72 int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
73 u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs);
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| H A D | cm33xx.c | 81 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
86 static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs) argument
88 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
97 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
102 static bool _is_module_ready(u16 inst, u16 clkctrl_offs) argument
106 v = _clkctrl_idlest(inst, clkctrl_offs);
213 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
221 static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, argument
226 omap_test_timeout(_is_module_ready(inst, clkctrl_offs),
237 * @clkctrl_offs
244 am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, u8 bit_shift) argument
265 am33xx_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs) argument
284 am33xx_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) argument
[all...] |
| H A D | omap_hwmod_81xx_data.c | 25 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
94 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
169 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
196 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
238 .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL,
275 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
296 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
317 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
355 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
392 .clkctrl_offs
[all...] |
| H A D | cminst44xx.c | 80 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
85 static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs) argument
87 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
97 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
102 static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs) argument
106 v = _clkctrl_idlest(part, inst, clkctrl_offs);
266 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
274 static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, argument
279 omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs),
290 * @clkctrl_offs
297 omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, u8 bit_shift) argument
318 omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs) argument
337 omap4_cminst_module_disable(u8 part, u16 inst, u16 clkctrl_offs) argument
[all...] |
| H A D | cm_common.c | 125 * @clkctrl_offs: CM_CLKCTRL register offset for the module
127 * Enables clocks for a module identified by (@part, @inst, @clkctrl_offs)
131 int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs) argument
139 cm_ll_data->module_enable(mode, part, inst, clkctrl_offs);
147 * @clkctrl_offs: CM_CLKCTRL register offset for the module
149 * Disables clocks for a module identified by (@part, @inst, @clkctrl_offs)
153 int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) argument
161 cm_ll_data->module_disable(part, inst, clkctrl_offs);
165 u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs) argument
172 return cm_ll_data->xlate_clkctrl(part, inst, clkctrl_offs);
[all...] |
| H A D | omap_hwmod.h | 361 * @clkctrl_offs: offset of the PRCM clock control register
377 u16 clkctrl_offs; member in struct:omap_hwmod_omap4_prcm
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| H A D | omap_hwmod.c | 768 oh->prcm.omap4.clkctrl_offs);
1018 if (oh->prcm.omap4.clkctrl_offs)
1021 if (!oh->prcm.omap4.clkctrl_offs &&
1076 oh->clkdm->cm_inst, oh->prcm.omap4.clkctrl_offs);
1107 oh->prcm.omap4.clkctrl_offs, 0);
1666 oh->prcm.omap4.clkctrl_offs);
2711 oh->prcm.omap4.clkctrl_offs, 0);
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