Lines Matching refs:clkctrl_offs
81 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
86 static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs)
88 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
97 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
102 static bool _is_module_ready(u16 inst, u16 clkctrl_offs)
106 v = _clkctrl_idlest(inst, clkctrl_offs);
213 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
221 static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
226 omap_test_timeout(_is_module_ready(inst, clkctrl_offs),
237 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
244 static int am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
249 omap_test_timeout((_clkctrl_idlest(inst, clkctrl_offs) ==
261 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
266 u16 clkctrl_offs)
270 v = am33xx_cm_read_reg(inst, clkctrl_offs);
273 am33xx_cm_write_reg(v, inst, clkctrl_offs);
280 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
284 static void am33xx_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
288 v = am33xx_cm_read_reg(inst, clkctrl_offs);
290 am33xx_cm_write_reg(v, inst, clkctrl_offs);