Searched refs:clk_register_divider (Results 1 - 21 of 21) sorted by relevance

/linux-master/drivers/clk/zynq/
H A Dclkc.c138 clk_register_divider(NULL, div0_name, mux_name,
142 clk_register_divider(NULL, div1_name, div0_name,
194 clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
281 clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
325 clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
331 clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
338 clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
341 clk_register_divider(NULL, "dci_div1", "dci_div0",
390 clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
393 clk_register_divider(NUL
[all...]
/linux-master/drivers/clk/sunxi/
H A Dclk-sun8i-apb0.c37 clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg,
H A Dclk-a10-pll2.c62 prediv_clk = clk_register_divider(NULL, "pll2-prediv",
/linux-master/drivers/clk/renesas/
H A Dclk-emev2.c73 clk = clk_register_divider(NULL, np->name, parent_name, 0,
/linux-master/drivers/clk/tegra/
H A Dclk-tegra-super-gen4.c117 clk = clk_register_divider(NULL, "sclk", "sclk_mux",
141 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
156 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
H A Dclk-tegra20.c816 clk_register_divider(NULL, "dev1_osc_div", "clk_m",
822 clk_register_divider(NULL, "dev2_osc_div", "clk_m",
/linux-master/drivers/clk/pistachio/
H A Dclk.c99 clk = clk_register_divider(NULL, div[i].name, div[i].parent,
/linux-master/drivers/clk/spear/
H A Dspear6xx_clock.c155 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
282 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
H A Dspear3xx_clock.c429 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
563 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
/linux-master/drivers/clk/mmp/
H A Dclk.c160 clk = clk_register_divider(NULL, clks[i].name,
/linux-master/drivers/clk/microchip/
H A Dclk-pic32mzda.c192 clks[FRCDIVCLK] = clk_register_divider(&pdev->dev, "frcdiv_clk",
/linux-master/drivers/clk/keystone/
H A Dpll.c282 clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift,
/linux-master/drivers/gpu/drm/fsl-dcu/
H A Dfsl_dcu_drm_drv.c309 fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
/linux-master/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c239 return clk_register_divider(NULL, name, parent_name, clkflags,
/linux-master/sound/soc/mxs/
H A Dmxs-saif.c705 clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk",
/linux-master/drivers/clk/rockchip/
H A Dclk.c496 clk = clk_register_divider(NULL, list->name,
/linux-master/drivers/clk/ti/
H A Dadpll.c251 clock = clk_register_divider(d->dev, child_name, parent_name, 0,
/linux-master/drivers/clk/davinci/
H A Dpll.c560 return clk_register_divider(dev, name, OSCIN_CLK_NAME, 0, base + BPDIV,
/linux-master/drivers/clk/xilinx/
H A Dclk-xlnx-clock-wizard.c1130 clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_divider
/linux-master/include/linux/
H A Dclk-provider.h743 * clk_register_divider - register a divider clock with the clock framework
754 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \ macro
/linux-master/sound/soc/samsung/
H A Di2s.c1320 priv->clk_table[CLK_I2S_RCLK_PSR] = clk_register_divider(dev,

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