Searched refs:clk_index (Results 1 - 8 of 8) sorted by relevance
| /linux-master/sound/soc/fsl/ |
| H A D | fsl_asrc.c | 387 u32 clk_index[2], div[2]; local
465 clk_index[IN] = asrc_priv->clk_map[IN][config->inclk];
466 clk_index[OUT] = asrc_priv->clk_map[OUT][config->outclk];
469 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
483 inrate, clk_index[ideal ? OUT : IN]);
489 clk = asrc_priv->asrck_clk[clk_index[OUT]];
499 outrate, clk_index[OUT]);
525 ASRCSR_AICS(index, clk_index[IN]) |
526 ASRCSR_AOCS(index, clk_index[OUT]));
668 int clk_rate, clk_index; local
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| /linux-master/drivers/clk/bcm/ |
| H A D | clk-kona.c | 881 if (sel->clk_index == BAD_CLK_INDEX) {
889 sel->clk_index = index;
894 BUG_ON((u32)sel->clk_index >= sel->parent_count);
895 parent_sel = sel->parent_sel[sel->clk_index];
944 previous = sel->clk_index;
948 sel->clk_index = index;
959 sel->clk_index = previous; /* Revert the change */
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| H A D | clk-kona.h | 338 u8 clk_index; /* current selected index in parent_sel[] */ member in struct:bcm_clk_sel
347 .clk_index = BAD_CLK_INDEX, \
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| /linux-master/drivers/phy/ti/ |
| H A D | phy-j721e-wiz.c | 810 const struct wiz_clk_mux_sel *mux_sel, int clk_index)
835 output_clk_names[clk_index]);
842 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]);
862 wiz->output_clks[clk_index] = clk;
1051 int clk_index; local
1055 clk_index = TI_WIZ_PLL0_REFCLK;
1056 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) {
1057 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index);
1059 dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]);
809 wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field, const struct wiz_clk_mux_sel *mux_sel, int clk_index) argument
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| /linux-master/drivers/phy/cadence/ |
| H A D | phy-cadence-sierra.c | 753 int clk_index)
765 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), clk_names[clk_index]);
771 init->parent_data = pll_mux_parent_data[clk_index];
784 sp->clk_data.hws[clk_index] = &mux->hw;
786 sp->pll_clks[clk_index] = devm_clk_hw_get_clk(dev, &mux->hw,
787 clk_names[clk_index]);
798 int ret = 0, i, clk_index; local
800 clk_index = CDNS_SIERRA_PLL_CMNLC;
801 for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++, clk_index++) {
807 termen_field, clk_index);
749 cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp, struct regmap_field *pfdclk1_sel_field, struct regmap_field *plllc1en_field, struct regmap_field *termen_field, int clk_index) argument
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| /linux-master/drivers/gpu/drm/amd/pm/ |
| H A D | amdgpu_pm.c | 859 uint clk_index; local
872 for (clk_index = 0 ; clk_index < 6 ; clk_index++) {
873 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
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| /linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | navi10_ppt.c | 1226 uint32_t clk_index = 0; local
1228 clk_index = smu_cmn_to_asic_specific_index(smu,
1231 dpm_desc = &pptable->DpmDescriptor[clk_index];
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| H A D | sienna_cichlid_ppt.c | 1252 uint32_t clk_index = 0; local
1255 clk_index = smu_cmn_to_asic_specific_index(smu,
1258 dpm_desc = &table_member[clk_index];
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