Searched refs:chid (Results 1 - 25 of 74) sorted by relevance

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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dchid.c22 #include "chid.h"
25 nvkm_chid_put(struct nvkm_chid *chid, int id, spinlock_t *data_lock) argument
28 spin_lock_irq(&chid->lock);
30 chid->data[id] = NULL;
32 clear_bit(id, chid->used);
33 spin_unlock_irq(&chid->lock);
38 nvkm_chid_get(struct nvkm_chid *chid, void *data) argument
42 spin_lock_irq(&chid->lock);
43 cid = find_first_zero_bit(chid->used, chid
56 struct nvkm_chid *chid = container_of(kref, typeof(*chid), kref); local
67 struct nvkm_chid *chid = *pchid; local
77 nvkm_chid_ref(struct nvkm_chid *chid) argument
89 struct nvkm_chid *chid; local
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H A Drunl.c25 #include "chid.h"
185 struct nvkm_chid *chid = runl->chid; local
190 spin_lock_irqsave(&chid->lock, flags);
191 for_each_set_bit(id, chid->used, chid->nr) {
192 chan = chid->data[id];
197 spin_unlock(&chid->lock);
202 spin_unlock_irqrestore(&chid->lock, flags);
209 struct nvkm_chid *chid local
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H A Dnv04.c27 #include "chid.h"
49 u32 chid; local
56 chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->chid->mask;
57 if (chid == chan->id) {
80 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask);
274 nv04_fifo_swmthd(struct nvkm_device *device, u32 chid, u32 addr, u32 data) argument
293 handled = nvkm_sw_mthd(sw, chid, subc, mthd, data);
303 nv04_fifo_intr_cache_error(struct nvkm_fifo *fifo, u32 chid, u32 get) argument
329 !nv04_fifo_swmthd(device, chid, mth
354 nv04_fifo_intr_dma_pusher(struct nvkm_fifo *fifo, u32 chid) argument
413 u32 reassign, chid, get, sem; local
[all...]
H A Dnv40.c27 #include "chid.h"
131 int chid; local
155 chid = nvkm_rd32(device, 0x003204) & (fifo->chid->nr - 1);
156 if (chid == chan->id)
221 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->chid->mask);
H A Dr535.c25 #include "chid.h"
221 int chid; member in struct:r535_chan_userd
237 u32 chid = chan->userd.base / chan->func->userd->size; local
239 userd->used &= ~BIT(chid);
243 nvkm_chid_put(runl->chid, userd->chid, &chan->cgrp->lock);
262 u32 chid; local
271 chid = div_u64(ouserd, chan->func->userd->size);
275 if (userd->used & BIT(chid))
291 userd->chid
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H A Drunq.h12 bool (*intr_1_ctxnotvalid)(struct nvkm_runq *, int chid);
H A Dbase.c26 #include "chid.h"
181 case NV_DEVICE_HOST_CHANNELS: *data = fifo->chid ? fifo->chid->nr : 0; return 0;
225 if (!fifo->chid) {
228 *data = runl->chid->nr;
309 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, fifo->chid->nr *
350 nvkm_chid_unref(&fifo->chid);
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dramht.h9 int chid; member in struct:nvkm_ramht_data
26 int chid, int addr, u32 handle, u32 context);
29 nvkm_ramht_search(struct nvkm_ramht *, int chid, u32 handle);
/linux-master/drivers/gpu/drm/nouveau/nvkm/core/
H A Dramht.c27 nvkm_ramht_hash(struct nvkm_ramht *ramht, int chid, u32 handle) argument
36 hash ^= chid << (ramht->bits - 4);
41 nvkm_ramht_search(struct nvkm_ramht *ramht, int chid, u32 handle) argument
45 co = ho = nvkm_ramht_hash(ramht, chid, handle);
47 if (ramht->data[co].chid == chid) {
61 int chid, int addr, u32 handle, u32 context)
68 data->chid = chid;
75 data->chid
60 nvkm_ramht_update(struct nvkm_ramht *ramht, int co, struct nvkm_object *object, int chid, int addr, u32 handle, u32 context) argument
107 nvkm_ramht_insert(struct nvkm_ramht *ramht, struct nvkm_object *object, int chid, int addr, u32 handle, u32 context) argument
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgp102.c38 int ctrl = chan->chid.ctrl;
39 int user = chan->chid.user;
148 gp102_disp_intr_error(struct nvkm_disp *disp, int chid) argument
152 u32 mthd = nvkm_rd32(device, 0x6111f0 + (chid * 12));
153 u32 data = nvkm_rd32(device, 0x6111f4 + (chid * 12));
154 u32 unkn = nvkm_rd32(device, 0x6111f8 + (chid * 12));
156 nvkm_error(subdev, "chid %d mthd %04x data %08x %08x %08x\n",
157 chid, (mthd & 0x0000ffc), data, mthd, unkn);
159 if (chid < ARRAY_SIZE(disp->chan)) {
162 nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERRO
[all...]
H A Dgf119.c507 const u32 mask = 0x00000001 << chan->chid.user;
522 int ctrl = chan->chid.ctrl;
523 int user = chan->chid.user;
541 int ctrl = chan->chid.ctrl;
542 int user = chan->chid.user;
570 return nvkm_ramht_insert(chan->disp->ramht, object, chan->chid.user, -9, handle,
571 chan->chid.user << 27 | 0x00000001);
579 int ctrl = chan->chid.ctrl;
580 int user = chan->chid.user;
601 int ctrl = chan->chid
1069 gf119_disp_intr_error(struct nvkm_disp *disp, int chid) argument
1111 int chid = __ffs(stat); stat &= ~(1 << chid); local
1120 int chid = ffs(stat) - 1; local
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H A Dchan.c178 if (disp->chan[chan->chid.user] == chan)
179 disp->chan[chan->chid.user] = NULL;
230 chan->chid.ctrl = user->ctrl + args->v0.id;
231 chan->chid.user = user->user + args->v0.id;
241 if (disp->chan[chan->chid.user]) {
245 disp->chan[chan->chid.user] = chan;
H A Dgv100.c336 return 0x690000 + ((chan->chid.user - 1) * 0x1000);
343 const u32 soff = (chan->chid.ctrl - 1) * 0x04;
356 return nvkm_ramht_insert(chan->disp->ramht, object, chan->chid.user, -9, handle,
357 chan->chid.user << 25 | 0x00000040);
364 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000;
365 const u32 coff = chan->chid.ctrl * 0x04;
377 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000;
378 const u32 poff = chan->chid.ctrl * 0x10;
379 const u32 coff = chan->chid.ctrl * 0x04;
558 const u32 soff = (chan->chid
894 gv100_disp_exception(struct nvkm_disp *disp, int chid) argument
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/linux-master/net/smc/
H A Dsmc_ism.h69 static inline bool __smc_ism_is_emulated(u16 chid) argument
77 return ((chid & 0xFF00) == 0xFF00);
82 u16 chid = smcd->ops->get_chid(smcd); local
84 return __smc_ism_is_emulated(chid);
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/engine/
H A Dsw.h13 bool nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data);
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv20.h28 int chid; member in struct:nv20_gr_chan
H A Dnv20.c24 nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4);
36 int chid = -1; local
40 chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;
41 if (chan->chid == chid) {
54 nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
86 chan->chid = fifoch->id;
96 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
190 u32 chid = (addr & 0x01f00000) >> 20; local
199 chan = nvkm_chan_get_chid(&gr->base.engine, chid,
[all...]
H A Dnv10.c402 int chid; member in struct:nv10_gr_chan
552 int chid = nvkm_rd32(device, 0x400148) >> 24; local
553 if (chid < ARRAY_SIZE(gr->chan))
554 chan = gr->chan[chid];
812 nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst) argument
861 0x2c000000 | chid << 20 | subchan << 16 | 0x18c);
883 nv10_gr_load_context(struct nv10_gr_chan *chan, int chid) argument
901 nv10_gr_load_dma_vtxbuf(chan, chid, inst);
904 nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24);
937 int chid; local
1090 u32 chid = (addr & 0x01f00000) >> 20; local
[all...]
H A Dnv04.c362 int chid; member in struct:nv04_gr_chan
1077 int chid = nvkm_rd32(device, NV04_PGRAPH_CTX_USER) >> 24; local
1078 if (chid < ARRAY_SIZE(gr->chan))
1079 chan = gr->chan[chid];
1085 nv04_gr_load_context(struct nv04_gr_chan *chan, int chid) argument
1094 nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24);
1119 int chid; local
1129 chid = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f;
1130 next = gr->chan[chid];
1132 nv04_gr_load_context(next, chid);
1281 u32 chid = (addr & 0x0f000000) >> 24; local
[all...]
/linux-master/drivers/gpu/drm/nouveau/include/nvif/
H A Dif0020.h24 __u16 chid; member in struct:nvif_chan_args::nvif_chan_v0
/linux-master/drivers/gpu/drm/nouveau/include/nvrm/535.113.01/nvidia/generated/
H A Dg_rpc-structures.h110 NvU32 chid; member in struct:rpc_rc_triggered_v17_02
120 NvU32 chid; member in struct:rpc_os_error_log_v17_00
/linux-master/drivers/bus/mhi/
H A Dcommon.h126 #define MHI_TRE_CMD_RESET_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
133 #define MHI_TRE_CMD_STOP_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
140 #define MHI_TRE_CMD_START_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
152 #define MHI_TRE_EV_DWORD1(chid, type) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
/linux-master/drivers/dma/qcom/
H A Dgpi.c91 #define GPII_n_CH_CMD(opcode, chid) \
93 FIELD_PREP(GPII_n_CH_CMD_CHID, chid))
140 #define GPII_n_EV_CMD(opcode, chid) \
142 FIELD_PREP(GPII_n_EV_CMD_CHID, chid))
246 u8 chid; member in struct:xfer_compl_event
257 u8 chid; member in struct:immediate_data_event
267 u8 chid; member in struct:qup_notif_event
487 u32 chid; member in struct:gchan
689 u32 chid = MAX_CHANNELS_PER_GPII; local
697 chid
768 u32 chid, state; local
939 u32 chid; local
1021 u32 chid; local
1097 u32 chid, type; local
1183 u32 chid = gpi_event->xfer_compl_event.chid; local
1274 u32 chid = chan->chid; local
2113 u32 seid, chid; local
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/sw/
H A Dbase.c30 nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data) argument
38 if (chan->fifo->id == chid) {
/linux-master/drivers/gpu/drm/nouveau/
H A Dnouveau_chan.h23 int chid; member in struct:nouveau_channel

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