| /linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_mst_types.h | 78 int bpp_x16; member in struct:dsc_mst_fairness_vars
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| H A D | amdgpu_dm_mst_types.c | 845 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
961 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
982 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
1018 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16
1055 vars[next_index].bpp_x16 = 0;
1153 vars[i + k].bpp_x16 = 0;
1172 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
1180 vars[i + k].bpp_x16 = 0;
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| /linux-master/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dsc.h | 89 uint32_t bpp_x16, uint32_t num_slices_h, bool is_dp);
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| /linux-master/drivers/gpu/drm/amd/display/dc/dsc/ |
| H A D | dc_dsc.c | 594 struct fixed31_32 bpp_x16; local
601 bpp_x16 = dc_fixpt_mul_int(effective_bandwidth_in_kbps, 10);
602 bpp_x16 = dc_fixpt_div_int(bpp_x16, timing->pix_clk_100hz);
603 bpp_x16 = dc_fixpt_from_int(dc_fixpt_floor(dc_fixpt_mul_int(bpp_x16, bpp_increment_div)));
604 bpp_x16 = dc_fixpt_div_int(bpp_x16, bpp_increment_div);
605 bpp_x16 = dc_fixpt_mul_int(bpp_x16, 1
1110 dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing, uint32_t bpp_x16, uint32_t num_slices_h, bool is_dp) argument
[all...] |
| /linux-master/drivers/gpu/drm/i915/display/ |
| H A D | intel_display_types.h | 2166 static inline int to_bpp_int(int bpp_x16) argument
2168 return bpp_x16 >> 4;
2171 static inline int to_bpp_frac(int bpp_x16) argument
2173 return bpp_x16 & 0xf;
2177 #define BPP_X16_ARGS(bpp_x16) to_bpp_int(bpp_x16), (to_bpp_frac(bpp_x16) * 625)
2179 static inline int to_bpp_int_roundup(int bpp_x16) argument
2181 return (bpp_x16 + 0xf) >> 4;
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| H A D | intel_dp.h | 118 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
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| H A D | intel_dp_mst.c | 77 bool ssc, bool dsc, int bpp_x16)
101 bpp_x16,
114 int bpp_x16,
121 intel_link_compute_m_n(bpp_x16, crtc_state->lane_count,
130 static int intel_dp_mst_calc_pbn(int pixel_clock, int bpp_x16, int bw_overhead) argument
133 intel_dp_effective_data_rate(pixel_clock, bpp_x16, bw_overhead);
75 intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state, const struct intel_connector *connector, bool ssc, bool dsc, int bpp_x16) argument
111 intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state, const struct intel_connector *connector, int overhead, int bpp_x16, struct intel_link_m_n *m_n) argument
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| H A D | intel_dp.c | 392 * @bpp_x16: bits per pixel .4 fixed point format
398 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, argument
401 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
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| /linux-master/drivers/gpu/drm/display/ |
| H A D | drm_dp_helper.c | 4060 static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16, argument
4063 int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
4070 int bpp_x16, int symbol_size, bool is_mst)
4074 bpp_x16, symbol_size, is_mst);
4085 * @bpp_x16: bits per pixel in .4 binary fixed point
4097 * - @bpp_x16 color depth
4107 int bpp_x16, unsigned long flags)
4114 if (lane_count == 0 || hactive == 0 || bpp_x16 == 0) {
4115 DRM_DEBUG_KMS("Invalid BW overhead params: lane_count %d, hactive %d, bpp_x16 %d.%04d\n",
4117 bpp_x16 >>
4069 drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count, int bpp_x16, int symbol_size, bool is_mst) argument
4105 drm_dp_bw_overhead(int lane_count, int hactive, int dsc_slice_count, int bpp_x16, unsigned long flags) argument
[all...] |
| /linux-master/include/drm/display/ |
| H A D | drm_dp_helper.h | 820 int bpp_x16, unsigned long flags);
|