Searched refs:a1 (Results 1 - 25 of 33) sorted by path

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/broadcom-cfe-1.4.2/cfe/api/
H A Dcfe_api.c111 cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1) argument
124 xiocb.plist.xiocb_cpuctl.a1_val = a1;
H A Dcfe_api.h170 int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1);
/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/bcmsb/src/
H A Dsbmemc.S88 * a1: x x x sdr/ddr flag
126 and a1,v1,M_SBID_CR
127 srl a1,a1,S_SBID_CR
128 beq a1,K_CR_MEMC,read_nvram
131 bne a1,(M_SBID_CR >> S_SBID_CR),1b # XXX No bus error?
392 * Uses a1, t7, t8, t9 (here and by calling sb_core_reset)
400 li a1,0
402 li a1,MEMC_CONFIG_INIT
403 or a1,a
[all...]
/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/sibyte/include/
H A Dsbmips.h187 #define a1 $5 macro
/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/sibyte/src/
H A Dsb1250_memcpy.S125 #define src a1
/broadcom-cfe-1.4.2/cfe/arch/mips/common/src/
H A Dapientry.S112 * a1 - pointer to IOCB to execute
157 lw t0,R_XIOCB_FCODE(a1)
159 lw t0,R_XIOCB_FLAGS(a1)
178 lw a0,R_XIOCB_XSTAT(a1) # Exit status
215 move a0,a1 # A0 points at IOCB
502 * a1,a2 - start/end of range for "range invalidate" operations
H A Ddev_flash_all.S72 * a1 - flashbase - base (phys addr) of flash area
81 #define flashbase a1
H A Dexception.S266 SR a1,(v0)
367 SREG a1,XGR_A1(k1)
420 move a1,k1 # Pass frame to exception handler
441 LREG a1,XGR_A1(k1)
H A Dinit_mips.S976 li a1,0
1024 * a1 - entry vector
1079 move a1,zero # A1 = 0
H A Dinit_ram.S389 li a1,0
416 * a1 - entry vector
468 move a1,zero # A1 = 0
H A Dlib_hssubr.S105 sb a1,(a0)
114 sh a1,(a0)
123 sw a1,(a0)
133 sd a1,(a0)
163 lbu t0,0(a1) /* copying one byte at a time */
166 ADDPTR a1,a1,1
193 sb a1,0(a0)
H A Dlib_physio.S155 PHYSOP(sb,a1)
163 PHYSOP(sh,a1)
171 PHYSOP(sw,a1)
179 PHYSOP(sd,a1)
H A Dlib_setjmp.S92 move v0,a1
H A Dzipstart_entry.S127 SREG a1,XGR_A1(k1)
175 move a1,k1 # Pass frame to exception handler
190 LREG a1,XGR_A1(k1)
H A Dzipstart_init.S493 li a1,0
544 * a1 -
594 move a1,zero
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/
H A Dbcm1480_altcpu.S628 * a1 - pointer to start parameters (four 64-bit values)
665 ld t2,R_CPUSTART_GPVAL(a1)
668 ld t2,R_CPUSTART_SPVAL(a1)
671 ld t2,R_CPUSTART_A1VAL(a1)
674 ld t2,R_CPUSTART_PCVAL(a1) /* this one actually starts the CPU */
872 ld a1,R_CPU_ARG(t0) # Load user argument (A1)
H A Dbcm1480_cpu.S281 move t0,a1
295 move t0,a1
H A Dbcm1480_ircpoll.S369 * a1 SR bits to be set
384 or t0,t0,a1
H A Dbcm1480_l1cache.S222 * a1 - length of buffer
232 sub a1,a1,L1CACHE_LINESIZE
233 bge a1,zero,1b
247 * a1 - length of buffer
257 sub a1,a1,L1CACHE_LINESIZE
258 bge a1,zero,1b
H A Dsb1_cpuinit.S87 move a1,zero
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcmcore/include/
H A Dsbmips32.h137 #define a1 $5 macro
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcmcore/src/
H A Dbcmcore_cpuinit.S375 move t0,a1
389 move t0,a1
H A Dbcmcore_ircpoll.S122 mfc0 a1, C0_SR
123 and a0, a0, a1
263 * a1 SR bits to be set
278 or t0,t0,a1
H A Dbcmcore_l1cache.S414 * a1 - length
420 * a0, a1, t0, t1
425 beq a1,zero,2f
431 add a1,a0,a1
433 addi a1,a1,LINESIZE-1
434 and a1,a1,t0
447 bne a0,a1,
[all...]
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/
H A Ddiag_l2cache.S548 #define R_BG_PAT0_1 a1
1277 #define R_ECC_PAT0_1 a1
1753 #define R_PAT0_1 a1

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