Lines Matching refs:a1
88 * a1: x x x sdr/ddr flag
126 and a1,v1,M_SBID_CR
127 srl a1,a1,S_SBID_CR
128 beq a1,K_CR_MEMC,read_nvram
131 bne a1,(M_SBID_CR >> S_SBID_CR),1b # XXX No bus error?
392 * Uses a1, t7, t8, t9 (here and by calling sb_core_reset)
400 li a1,0
402 li a1,MEMC_CONFIG_INIT
403 or a1,a1,t0
404 sw a1,MEMC_CONFIG(a0)
406 li a1,MEMC_DRAMTIM25_INIT # Assume CAS latency of 2.5
410 li a1,MEMC_DRAMTIM2_INIT # CAS latency is 2
412 sw a1,MEMC_DRAMTIM(a0)
415 sll a1,t8,8 # Replicate rd ncdl 4 times
416 or a1,a1,t8
417 sll t8,a1,16
418 or t8,t8,a1
419 li a1,MEMC_RDNCDLCOR_INIT
420 or a1,a1,t8
421 sw a1,MEMC_RDNCDLCOR(a0)
423 li a1,MEMC_WRNCDLCOR_INIT # If rev0, 2:
426 li a1,MEMC_1_WRNCDLCOR_INIT # rev1
429 or a1,a1,t8
430 sw a1,MEMC_WRNCDLCOR(a0)
432 li a1,MEMC_DQSGATENCDL_INIT
434 or a1,a1,t8
435 sw a1,MEMC_DQSGATENCDL(a0)
437 li a1,MEMC_MISCDLYCTL_INIT # If rev0, 2:
440 li a1,MEMC_1_MISCDLYCTL_INIT # rev1
442 sw a1,MEMC_MISCDLYCTL(a0)
444 li a1,MEMC_NCDLCTL_INIT
445 sw a1,MEMC_NCDLCTL(a0)
447 li a1,MEMC_CONTROL_INIT0
448 sw a1,MEMC_CONTROL(a0)
450 li a1,MEMC_CONTROL_INIT1
451 sw a1,MEMC_CONTROL(a0)
453 li a1,MEMC_MODEBUF_INIT0
454 sw a1,MEMC_MODEBUF(a0)
456 li a1,MEMC_CONTROL_INIT2
457 sw a1,MEMC_CONTROL(a0)
459 li a1,MEMC_MODEBUF_INIT1
460 or a1,a1,t1
461 sw a1,MEMC_MODEBUF(a0)
463 li a1,MEMC_CONTROL_INIT3
464 sw a1,MEMC_CONTROL(a0)
466 li a1,MEMC_CONTROL_INIT4
467 sw a1,MEMC_CONTROL(a0)
469 li a1,MEMC_CONTROL_INIT5
470 sw a1,MEMC_CONTROL(a0)
471 lw a1,MEMC_CONTROL(a0)
472 lw a1,MEMC_CONTROL(a0)
473 lw a1,MEMC_CONTROL(a0)
475 li a1,MEMC_CONTROL_INIT5
476 sw a1,MEMC_CONTROL(a0)
477 lw a1,MEMC_CONTROL(a0)
478 lw a1,MEMC_CONTROL(a0)
479 lw a1,MEMC_CONTROL(a0)
481 li a1,MEMC_REFRESH_INIT
482 sw a1,MEMC_REFRESH(a0)
484 li a1,MEMC_MODEBUF_INIT2
485 or a1,a1,t1
486 sw a1,MEMC_MODEBUF(a0)
488 li a1,MEMC_CONTROL_INIT6
489 sw a1,MEMC_CONTROL(a0)
491 li a1,MEMC_CONTROL_INIT7
492 sw a1,MEMC_CONTROL(a0)
498 1: lw a1,R_SBIDLOW(a0)
499 lw a1,R_SBIDHIGH(a0)
660 * Uses a1, t7, t8, t9 (here and by calling sb_core_reset)
668 li a1,0x40
671 li a1,MEMC_SD_CONFIG_INIT
672 or a1,a1,t0
673 sw a1,MEMC_CONFIG(a0)
675 li a1,MEMC_SD_DRAMTIM3_INIT # Assume CAS latency of 3
679 li a1,MEMC_SD_DRAMTIM2_INIT # CAS latency is 2
681 sw a1,MEMC_DRAMTIM(a0)
690 sll a1,t8,8 # .. replicate it 4 times
691 or a1,a1,t8
692 sll t8,a1,16
693 or t8,t8,a1
694 li a1,MEMC_SD_RDNCDLCOR_INIT
695 or a1,a1,t8
696 sw a1,MEMC_RDNCDLCOR(a0)
698 li a1,MEMC_SD1_WRNCDLCOR_INIT # rev1
701 li a1,MEMC_SD_WRNCDLCOR_INIT # rev0, 2
712 or a1,a1,t8
713 sw a1,MEMC_WRNCDLCOR(a0)
716 sll a1,t8,28
719 or t8,t8,a1
720 li a1,MEMC_SD_MISCDLYCTL_INIT
723 li a1,MEMC_SD1_MISCDLYCTL_INIT # rev1:
725 or a1,a1,t8
726 sw a1,MEMC_MISCDLYCTL(a0)
728 li a1,MEMC_SD_CONTROL_INIT0
729 sw a1,MEMC_CONTROL(a0)
731 li a1,MEMC_SD_CONTROL_INIT1
732 sw a1,MEMC_CONTROL(a0)
734 li a1,MEMC_SD_CONTROL_INIT2
735 sw a1,MEMC_CONTROL(a0)
736 lw a1,MEMC_CONTROL(a0)
737 lw a1,MEMC_CONTROL(a0)
738 lw a1,MEMC_CONTROL(a0)
740 li a1,MEMC_SD_CONTROL_INIT2
741 sw a1,MEMC_CONTROL(a0)
742 lw a1,MEMC_CONTROL(a0)
743 lw a1,MEMC_CONTROL(a0)
744 lw a1,MEMC_CONTROL(a0)
746 li a1,MEMC_SD_CONTROL_INIT2
747 sw a1,MEMC_CONTROL(a0)
748 lw a1,MEMC_CONTROL(a0)
749 lw a1,MEMC_CONTROL(a0)
750 lw a1,MEMC_CONTROL(a0)
752 li a1,MEMC_SD_REFRESH_INIT
753 sw a1,MEMC_REFRESH(a0)
755 li a1,MEMC_SD_MODEBUF_INIT
756 or a1,a1,t1
757 sw a1,MEMC_MODEBUF(a0)
759 li a1,MEMC_SD_CONTROL_INIT3
760 sw a1,MEMC_CONTROL(a0)
762 li a1,MEMC_SD_CONTROL_INIT4
763 sw a1,MEMC_CONTROL(a0)
766 1: lw a1,R_SBIDLOW(a0)
767 lw a1,R_SBIDHIGH(a0)
812 * Uses a1, a2, a3 & t5
816 li a1,0xa0000000
819 add a1,a1,a2
823 sw a2,0(a1)
825 sw a3,4(a1)
827 lw t5,0(a1)
830 lw t5,4(a1)
836 sw a2,0(a1)
838 sw a3,4(a1)
840 lw t5,0(a1)
843 lw t5,4(a1)
849 sw a2,0(a1)
851 sw a3,4(a1)
853 lw t5,0(a1)
856 lw t5,4(a1)
865 sw a2,0(a1)
867 sw a3,4(a1)
869 lw t5,0(a1)
872 lw t5,4(a1)
878 sw a2,0(a1)
880 sw a3,4(a1)
882 lw t5,0(a1)
885 lw t5,4(a1)
899 * by a1.
902 * a1: 0x40 if a6 needs to be 1, 0 otherwise
922 bne t8,a1,alt_core_reset