Searched refs:__raw_writel (Results 1 - 25 of 427) sorted by relevance

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/linux-master/arch/sh/boards/mach-sh7763rdp/
H A Dirq.c28 __raw_writel(1 << 25, INTC_INT2MSKCR);
31 __raw_writel((__raw_readl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000,
35 __raw_writel(1 << 17, INTC_INT2MSKCR1);
38 __raw_writel(1 << 16, INTC_INT2MSKCR1);
41 __raw_writel(1 << 8, INTC_INT2MSKCR);
/linux-master/arch/mips/alchemy/common/
H A Dvss.c27 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */
30 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */
34 __raw_writel(0x01, base + VSS_FTR);
36 __raw_writel(0x03, base + VSS_FTR);
38 __raw_writel(0x07, base + VSS_FTR);
40 __raw_writel(0x0f, base + VSS_FTR);
43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */
46 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */
49 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */
58 __raw_writel(
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H A Dusb.c112 __raw_writel(r, base + USB_DWC_CTRL2);
118 __raw_writel(r, base + USB_DWC_CTRL2);
128 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */
134 __raw_writel(r, base + USB_DWC_CTRL3);
141 __raw_writel(r, base + USB_INT_ENABLE);
145 __raw_writel(0, base + USB_DWC_CTRL7);
150 __raw_writel(r, base + USB_INT_ENABLE);
156 __raw_writel(r, base + USB_DWC_CTRL3);
170 __raw_writel(r, base + USB_DWC_CTRL3);
175 __raw_writel(
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H A Dirq.c293 __raw_writel(1 << bit, base + IC_MASKSET);
294 __raw_writel(1 << bit, base + IC_WAKESET);
303 __raw_writel(1 << bit, base + IC_MASKSET);
304 __raw_writel(1 << bit, base + IC_WAKESET);
313 __raw_writel(1 << bit, base + IC_MASKCLR);
314 __raw_writel(1 << bit, base + IC_WAKECLR);
323 __raw_writel(1 << bit, base + IC_MASKCLR);
324 __raw_writel(1 << bit, base + IC_WAKECLR);
337 __raw_writel(1 << bit, base + IC_FALLINGCLR);
338 __raw_writel(
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/linux-master/arch/arm/mach-s3c/
H A Dpm-core-s3c64xx.h30 __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
55 __raw_writel(0, S3C64XX_SLPEN);
65 __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
/linux-master/arch/sh/mm/
H A Dtlb-pteaex.c32 __raw_writel(vpn, MMU_PTEH);
35 __raw_writel(get_asid(), MMU_PTEAEX);
47 __raw_writel(pte.pte_high, MMU_PTEA);
56 __raw_writel(pteval, MMU_PTEL);
73 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
74 __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
75 __raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
76 __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
98 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
101 __raw_writel(
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H A Dtlb-sh4.c30 __raw_writel(vpn, MMU_PTEH);
42 __raw_writel(pte.pte_high, MMU_PTEA);
48 __raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
58 __raw_writel(pteval, MMU_PTEL);
78 __raw_writel(data, addr);
100 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
103 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
/linux-master/arch/arm/mach-pxa/
H A Dsmemc.c37 __raw_writel(msc[0], MSC0);
38 __raw_writel(msc[1], MSC1);
39 __raw_writel(sxcnfg, SXCNFG);
40 __raw_writel(memclkcfg, MEMCLKCFG);
41 __raw_writel(csadrcfg[0], CSADRCFG0);
42 __raw_writel(csadrcfg[1], CSADRCFG1);
43 __raw_writel(csadrcfg[2], CSADRCFG2);
44 __raw_writel(csadrcfg[3], CSADRCFG3);
46 __raw_writel(0x2, CSMSADRCFG);
65 __raw_writel(
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H A Dgeneric.c62 __raw_writel(mcmem, MCMEM(sock));
63 __raw_writel(mcatt, MCATT(sock));
64 __raw_writel(mcio, MCIO(sock));
72 __raw_writel(0, MECR);
79 __raw_writel(MECR_CIT, MECR);
83 __raw_writel(MECR_CIT | MECR_NOS, MECR);
/linux-master/arch/mips/sgi-ip22/
H A Dip22-nvram.c36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
64 __raw_writel(__raw_read
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/linux-master/include/linux/mlx5/
H A Ddoorbell.h55 __raw_writel((__force u32) val[0], dest);
56 __raw_writel((__force u32) val[1], dest + 4);
/linux-master/arch/mips/include/asm/mach-rc32434/
H A Ddma_v.h30 __raw_writel(0, &ch->dmac);
33 __raw_writel(0, &ch->dmas);
44 __raw_writel(0, &ch->dmandptr);
45 __raw_writel(dma_addr, &ch->dmadptr);
50 __raw_writel(dma_addr, &ch->dmandptr);
/linux-master/arch/arm/mach-mmp/
H A Dtime.c50 __raw_writel(1, mmp_timer_base + TMR_CVWR(1));
70 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
75 __raw_writel(0x02, mmp_timer_base + TMR_CER);
92 __raw_writel(0x02, mmp_timer_base + TMR_CER);
97 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
98 __raw_writel(0x01, mmp_timer_base + TMR_IER(0));
103 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
108 __raw_writel(0x03, mmp_timer_base + TMR_CER);
121 __raw_writel(0x00, mmp_timer_base + TMR_IER(0));
153 __raw_writel(
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/linux-master/arch/mips/kernel/
H A Dcevt-txx9.c63 __raw_writel(TCR_BASE, &tmrptr->tcr);
64 __raw_writel(0, &tmrptr->tisr);
65 __raw_writel(TIMER_CCD, &tmrptr->ccdr);
66 __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr);
67 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);
68 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
83 __raw_writel(TCR_BASE, &tmrptr->tcr);
85 __raw_writel(0, &tmrptr->tisr);
96 __raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE, &tmrptr->itmr);
98 __raw_writel(((u6
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/linux-master/arch/sh/kernel/cpu/sh4a/
H A Dubc.c34 __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx));
35 __raw_writel(info->address, UBC_CAR(idx));
40 __raw_writel(0, UBC_CBR(idx));
41 __raw_writel(0, UBC_CAR(idx));
50 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE,
59 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE,
82 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR);
112 __raw_writel(0, UBC_CBCR);
115 __raw_writel(0, UBC_CAMR(i));
116 __raw_writel(
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H A Dsmp-shx3.c36 __raw_writel(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
51 __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu));
87 __raw_writel(entry_point, RESET_REG(cpu));
89 __raw_writel(virt_to_phys(entry_point), RESET_REG(cpu));
92 __raw_writel(STBCR_MSTP, STBCR_REG(cpu));
98 __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu));
112 __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
117 __raw_writel(STBCR_MSTP, STBCR_REG(cpu));
120 __raw_writel(STBCR_RESET, STBCR_REG(cpu));
/linux-master/arch/sh/kernel/cpu/sh3/
H A Dprobe.c31 __raw_writel(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
33 __raw_writel(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
38 __raw_writel(data0, addr0);
41 __raw_writel(data2, addr1);
45 __raw_writel(data0&~SH_CACHE_VALID, addr0);
46 __raw_writel(data2&~SH_CACHE_VALID, addr1);
94 __raw_writel(CCR_CACHE_32KB, CCR3_REG);
96 __raw_writel(CCR_CACHE_16KB, CCR3_REG);
/linux-master/arch/mips/ath79/
H A Dcommon.c61 __raw_writel(0x1, flush_reg);
66 __raw_writel(0x1, flush_reg);
76 __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0);
77 __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4);
78 __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8);
79 __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc);
80 __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10);
81 __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14);
82 __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18);
83 __raw_writel(AR71XX_PCI_WIN7_OFF
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/linux-master/arch/arm/mach-lpc32xx/
H A Dserial.c110 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
117 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
118 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
123 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
127 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
131 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
132 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
136 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
142 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
147 __raw_writel(tm
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/linux-master/arch/arm/include/asm/
H A Dcti.h92 __raw_writel(val, base + CTIINEN + trig_in * 4);
96 __raw_writel(val, base + CTIOUTEN + trig_out * 4);
107 __raw_writel(0x1, cti->base + CTICONTROL);
118 __raw_writel(0, cti->base + CTICONTROL);
134 __raw_writel(val, base + CTIINTACK);
146 __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS);
158 __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS);
/linux-master/arch/sh/drivers/pci/
H A Dpci-sh7780.c127 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT);
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT);
154 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM);
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT);
200 __raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \
205 __raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \
231 __raw_writel(tmp, hose->reg_base + SH4_PCICR);
241 __raw_writel(tmp, hose->reg_base + SH4_PCICR);
258 __raw_writel(PCIECR_ENBL, PCIECR);
261 __raw_writel(SH4_PCICR_PREFI
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/linux-master/arch/mips/loongson32/common/
H A Dirq.c28 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
37 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
46 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
48 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
57 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
68 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
70 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
74 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
76 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
80 __raw_writel(__raw_read
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/linux-master/arch/mips/include/asm/mach-ralink/
H A Dralink_regs.h37 __raw_writel(val, rt_sysc_membase + reg);
49 __raw_writel(val | set, rt_sysc_membase + reg);
54 __raw_writel(val, rt_memc_membase + reg);
/linux-master/drivers/infiniband/hw/qib/
H A Dqib_pio_copy.c55 __raw_writel(*(const u32 *)src, dst);
62 __raw_writel(*src++, dst++);
/linux-master/arch/sh/include/asm/
H A Dmmu_context_32.h8 __raw_writel(asid, MMU_PTEAEX);
44 __raw_writel((unsigned long)pgd, MMU_TTB);

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