Lines Matching refs:__raw_writel

127 	__raw_writel(cmd, hose->reg_base + SH4_PCIAINT);
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT);
154 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM);
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT);
200 __raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \
205 __raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \
231 __raw_writel(tmp, hose->reg_base + SH4_PCICR);
241 __raw_writel(tmp, hose->reg_base + SH4_PCICR);
258 __raw_writel(PCIECR_ENBL, PCIECR);
261 __raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_PRST | PCICR_ENDIANNESS,
296 __raw_writel(SH4_PCICR_PREFIX | PCICR_ENDIANNESS,
307 __raw_writel(memphys + SZ_512M, chan->reg_base + SH4_PCILAR1);
308 __raw_writel((((memsize - SZ_512M) - SZ_1M) & 0x1ff00000) | 1,
315 __raw_writel(0, chan->reg_base + SH4_PCILAR1);
316 __raw_writel(0, chan->reg_base + SH4_PCILSR1);
323 __raw_writel(memphys, chan->reg_base + SH4_PCILAR0);
324 __raw_writel(((memsize - SZ_1M) & 0x1ff00000) | 1,
337 __raw_writel(0, chan->reg_base + SH7780_PCICSCR0);
338 __raw_writel(0, chan->reg_base + SH7780_PCICSAR0);
339 __raw_writel(0, chan->reg_base + SH7780_PCICSCR1);
340 __raw_writel(0, chan->reg_base + SH7780_PCICSAR1);
367 __raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
369 __raw_writel(res->start, chan->reg_base + SH7780_PCIMBR(i - 1));
375 __raw_writel(0, chan->reg_base + PCI_BASE_ADDRESS_0);
376 __raw_writel(0, chan->reg_base + SH7780_PCIIOBR);
377 __raw_writel(0, chan->reg_base + SH7780_PCIIOBMR);
387 __raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO |