/freebsd-11-stable/sys/arm/freescale/vybrid/ |
H A D | vf_dcu4.c | 230 WRITE4(sc, DCU_INT_STATUS, reg); 295 WRITE4(sc, DCU_DISP_SIZE, reg); 300 WRITE4(sc, DCU_HSYN_PARA, reg); 305 WRITE4(sc, DCU_VSYN_PARA, reg); 307 WRITE4(sc, DCU_BGND, 0); 308 WRITE4(sc, DCU_DIV_RATIO, panel->clk_div); 311 WRITE4(sc, DCU_SYNPOL, reg); 317 WRITE4(sc, DCU_THRESHOLD, reg); 320 WRITE4(sc, DCU_INT_MASK, 0xffffffff); 324 WRITE4(s [all...] |
H A D | vf_anadig.c | 142 WRITE4(sc, pll_ctrl, reg); 150 WRITE4(sc, pll_ctrl, reg); 170 WRITE4(sc, ANADIG_PLL4_CTRL, reg); 171 WRITE4(sc, ANADIG_PLL4_NUM, mfn); 172 WRITE4(sc, ANADIG_PLL4_DENOM, mfd); 210 WRITE4(sc, ANADIG_REG_3P0, reg); 215 WRITE4(sc, USB_MISC(0), reg); 219 WRITE4(sc, USB_MISC(1), reg);
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H A D | vf_spi.c | 170 WRITE4(sc, SPI_MCR, reg); 174 WRITE4(sc, SPI_RSER, reg); 178 WRITE4(sc, SPI_MCR, reg); 196 WRITE4(sc, SPI_CTAR0, reg); 201 WRITE4(sc, SPI_CTAR0, reg); 226 WRITE4(sc, SPI_PUSHR, wreg); 237 WRITE4(sc, SPI_SR, reg);
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H A D | vf_adc.c | 178 WRITE4(sc, ADC_HC0, reg); 215 WRITE4(sc, ADC_CFG, reg); 220 WRITE4(sc, ADC_GC, reg); 225 WRITE4(sc, ADC_HC0, reg);
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H A D | vf_common.h | 31 #define WRITE4(_sc, _reg, _val) \ macro
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H A D | vf_nfc.c | 200 WRITE4(sc, NFC_SECSZ, 2048); 221 WRITE4(sc, NFC_CFG, reg); 244 WRITE4(sc, NFC_CMD2, reg); 260 WRITE4(sc, NFC_CMD1, reg); 267 WRITE4(sc, NFC_CMD2, reg); 273 WRITE4(sc, NFC_CMD2, reg); 281 WRITE4(sc, NFC_CAR, reg); 291 WRITE4(sc, NFC_RAR, reg); 296 WRITE4(sc, NFC_CMD2, reg);
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/freebsd-11-stable/sys/arm/freescale/imx/ |
H A D | imx_gpt.c | 52 #define WRITE4(_sc, _r, _v) \ macro 57 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 59 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 203 WRITE4(sc, IMX_GPT_CR, 0); 204 WRITE4(sc, IMX_GPT_IR, 0); 214 WRITE4(sc, IMX_GPT_CR, ctlreg); 224 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR); 237 WRITE4(sc, IMX_GPT_PR, prescale); 240 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); 243 WRITE4(s [all...] |
H A D | imx6_sdma.c | 68 #define WRITE4(_sc, _reg, _val) \ macro 95 WRITE4(sc, SDMAARM_INTR, pending); 113 WRITE4(sc, SDMAARM_HSTART, (1 << i)); 138 WRITE4(sc, SDMAARM_HSTART, (1 << chn)); 150 WRITE4(sc, SDMAARM_STOP_STAT, (1 << chn)); 219 WRITE4(sc, SDMAARM_EVTOVR, reg); 227 WRITE4(sc, SDMAARM_HOSTOVR, reg); 235 WRITE4(sc, SDMAARM_DSPOVR, reg); 263 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1); 264 WRITE4(s [all...] |
H A D | imx6_audmux.c | 58 #define WRITE4(_sc, _reg, _val) \ macro 109 WRITE4(sc, AUDMUX_PTCR(audmux_port), reg); 113 WRITE4(sc, AUDMUX_PDCR(audmux_port), reg);
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/freebsd-11-stable/sys/dev/mmc/host/ |
H A D | dwmmc.c | 68 #define WRITE4(_sc, _reg, _val) \ macro 184 WRITE4(sc, SDMMC_CTRL, reg); 349 WRITE4(sc, SDMMC_RINTSTS, DWMMC_CMD_ERR_FLAGS); 356 WRITE4(sc, SDMMC_RINTSTS, DWMMC_DATA_ERR_FLAGS); 369 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_CMD_DONE); 374 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_ACD); 379 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_DTO); 384 WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_CD); 401 WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI | 403 WRITE4(s [all...] |
/freebsd-11-stable/sys/dev/hatm/ |
H A D | if_hatm.c | 514 WRITE4(sc, HE_REGO_RESET_CNTL, 0x00); 516 WRITE4(sc, HE_REGO_RESET_CNTL, 0xff); 549 WRITE4(sc, HE_REGO_HOST_CNTL, v); 588 WRITE4(sc, HE_REGO_LB_SWAP, v); 607 WRITE4(sc, HE_REGO_HOST_CNTL, val); 612 WRITE4(sc, HE_REGO_HOST_CNTL, val | readtab[i]); 619 WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++] | 623 WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++] | 630 WRITE4(sc, HE_REGO_HOST_CNTL, val); 636 WRITE4(s [all...] |
/freebsd-11-stable/sys/arm/samsung/exynos/ |
H A D | exynos5_usb_phy.c | 180 WRITE4(sc, USB_DRD_PHYREG0, 0); 187 WRITE4(sc, USB_DRD_PHYPARAM0, reg); 188 WRITE4(sc, USB_DRD_PHYRESUME, 0); 192 WRITE4(sc, USB_DRD_LINKSYSTEM, reg); 197 WRITE4(sc, USB_DRD_PHYPARAM1, reg); 201 WRITE4(sc, USB_DRD_PHYUTMICLKSEL, reg); 206 WRITE4(sc, USB_DRD_PHYTEST, reg); 208 WRITE4(sc, USB_DRD_PHYUTMI, PHYUTMI_OTGDISABLE); 221 WRITE4(sc, USB_DRD_PHYCLKRST, reg); 224 WRITE4(s [all...] |
H A D | exynos5_spi.c | 130 WRITE4(sc, FB_CLK_SEL, FB_CLK_180); 134 WRITE4(sc, CH_CFG, reg); 155 WRITE4(sc, CH_CFG, reg); 157 WRITE4(sc, CH_CFG, reg); 162 WRITE4(sc, CS_REG, reg); 186 WRITE4(sc, CS_REG, reg);
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H A D | exynos5_xhci.c | 166 WRITE4(esc, GCTL, GCTL_CORESOFTRESET); 167 WRITE4(esc, GUSB3PIPECTL(0), GUSB3PIPECTL_PHYSOFTRST); 168 WRITE4(esc, GUSB2PHYCFG(0), GUSB2PHYCFG_PHYSOFTRST); 174 WRITE4(esc, GUSB3PIPECTL(0), reg); 178 WRITE4(esc, GUSB2PHYCFG(0), reg); 182 WRITE4(esc, GCTL, reg); 196 WRITE4(esc, GCTL, reg); 202 WRITE4(esc, GCTL, reg);
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H A D | exynos5_pmu.c | 113 WRITE4(sc, EXYNOS5_PWR_USBHOST_PHY, PHY_POWER_ON); 130 WRITE4(sc, EXYNOS5_USBDRD_PHY_CTRL, PHY_POWER_ON); 137 WRITE4(sc, EXYNOS5420_USBDRD1_PHY_CTRL, PHY_POWER_ON);
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H A D | exynos5_common.h | 31 #define WRITE4(_sc, _reg, _val) \ macro
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H A D | exynos5_fimd.c | 264 WRITE4(sc,VIDCON0,reg); 281 WRITE4(sc, VIDW00ADD0B0, reg); 283 WRITE4(sc, VIDW00ADD1B0, reg); 284 WRITE4(sc, VIDW00ADD2, sc->sc_info.fb_stride); 288 WRITE4(sc,VIDOSD0B,reg); 291 WRITE4(sc,VIDOSD0C,reg); 296 WRITE4(sc,SHADOWCON,reg); 301 WRITE4(sc,WINCON0,reg); 304 WRITE4(sc, DPCLKCON, DPCLKCON_EN);
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/freebsd-11-stable/sys/arm/altera/socfpga/ |
H A D | socfpga_common.h | 36 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) macro
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H A D | socfpga_manager.c | 228 WRITE4(sc, FPGAMGR_CTRL, reg); 233 WRITE4(sc, FPGAMGR_CTRL, reg); 238 WRITE4(sc, FPGAMGR_CTRL, reg); 249 WRITE4(sc, FPGAMGR_CTRL, reg); 257 WRITE4(sc, GPIO_PORTA_EOI, PORTA_EOI_NS); 262 WRITE4(sc, FPGAMGR_CTRL, reg); 274 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); 277 WRITE4(sc, FPGAMGR_DCLKCNT, npulses); 283 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1); 314 WRITE4(s [all...] |
/freebsd-11-stable/sys/dev/xilinx/ |
H A D | axi_quad_spi.c | 69 #define WRITE4(_sc, _reg, _val) \ macro 143 WRITE4(sc, SPI_SRR, SRR_RESET); 148 WRITE4(sc, SPI_CR, reg); 149 WRITE4(sc, SPI_DGIER, 0); /* Disable interrupts */ 152 WRITE4(sc, SPI_CR, reg); 166 WRITE4(sc, SPI_DTR, out_buf[i]); 201 WRITE4(sc, SPI_SSR, reg); 212 WRITE4(sc, SPI_SSR, reg);
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/freebsd-11-stable/sys/dev/altera/pio/ |
H A D | pio.c | 63 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) macro 128 WRITE4(sc, PIO_OUTSET, bit); 130 WRITE4(sc, PIO_OUTCLR, bit); 142 WRITE4(sc, PIO_INT_MASK, mask); 143 WRITE4(sc, PIO_DIR, dir);
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/freebsd-11-stable/sys/mips/mediatek/ |
H A D | mtk_intr_gic.c | 107 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->gic_res[0], (_reg), (_val)) macro 127 WRITE4(sc, MTK_INTENA, (1u << (irq))); 134 WRITE4(sc, MTK_INTDIS, (1u << (irq))); 190 WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF); 193 WRITE4(sc, MTK_INTTRIG, 0x00000000); 196 WRITE4(sc, MTK_INTPOL, 0xFFFFFFFF); 202 WRITE4(sc, MTK_MAPPIN(i), MTK_PIN_BITS(0)); 203 WRITE4(sc, MTK_MAPVPE(i, 0), MTK_VPE_BITS(0));
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H A D | mtk_intr_v1.c | 105 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val) macro 125 WRITE4(sc, MTK_INTENA, (1u << (irq))); 132 WRITE4(sc, MTK_INTDIS, (1u << (irq))); 186 WRITE4(sc, MTK_INTDIS, 0x7FFFFFFF); 189 WRITE4(sc, MTK_INTENA, 0x80000000); 192 WRITE4(sc, MTK_INTTYPE, 0x00000000);
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H A D | mtk_intr_v2.c | 100 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val) macro 120 WRITE4(sc, MTK_INTENA, (1u << (irq))); 127 WRITE4(sc, MTK_INTDIS, (1u << (irq))); 181 WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF); 184 WRITE4(sc, MTK_INTENA, 0x00000000); 187 WRITE4(sc, MTK_INTTYPE, 0xFFFFFFFF);
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/freebsd-11-stable/sys/dev/dwc/ |
H A D | if_dwc.c | 84 #define WRITE4(_sc, _reg, _val) \ macro 280 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); 313 WRITE4(sc, OPERATION_MODE, reg); 318 WRITE4(sc, OPERATION_MODE, reg); 323 WRITE4(sc, MAC_CONFIGURATION, reg); 328 WRITE4(sc, OPERATION_MODE, reg); 337 WRITE4(sc, MMC_CONTROL, reg); 432 WRITE4(sc, OPERATION_MODE, reg); 434 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); 439 WRITE4(s [all...] |