1261413Sbr/*- 2261413Sbr * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3261413Sbr * All rights reserved. 4261413Sbr * 5261413Sbr * Redistribution and use in source and binary forms, with or without 6261413Sbr * modification, are permitted provided that the following conditions 7261413Sbr * are met: 8261413Sbr * 1. Redistributions of source code must retain the above copyright 9261413Sbr * notice, this list of conditions and the following disclaimer. 10261413Sbr * 2. Redistributions in binary form must reproduce the above copyright 11261413Sbr * notice, this list of conditions and the following disclaimer in the 12261413Sbr * documentation and/or other materials provided with the distribution. 13261413Sbr * 14261413Sbr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15261413Sbr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16261413Sbr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17261413Sbr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18261413Sbr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19261413Sbr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20261413Sbr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21261413Sbr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22261413Sbr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23261413Sbr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24261413Sbr * SUCH DAMAGE. 25261413Sbr */ 26261413Sbr 27261413Sbr/* 28261413Sbr * Vybrid Family Display Control Unit (DCU4) 29261413Sbr * Chapter 55, Vybrid Reference Manual, Rev. 5, 07/2013 30261413Sbr */ 31261413Sbr 32261413Sbr#include <sys/cdefs.h> 33261413Sbr__FBSDID("$FreeBSD: stable/11/sys/arm/freescale/vybrid/vf_dcu4.c 314503 2017-03-01 18:53:05Z ian $"); 34261413Sbr 35261413Sbr#include <sys/param.h> 36261413Sbr#include <sys/systm.h> 37261413Sbr#include <sys/bus.h> 38261413Sbr#include <sys/kernel.h> 39261413Sbr#include <sys/module.h> 40261413Sbr#include <sys/malloc.h> 41261413Sbr#include <sys/rman.h> 42261413Sbr#include <sys/timeet.h> 43261413Sbr#include <sys/timetc.h> 44261413Sbr#include <sys/watchdog.h> 45261413Sbr#include <sys/fbio.h> 46261413Sbr#include <sys/consio.h> 47261413Sbr#include <sys/eventhandler.h> 48262891Sbr#include <sys/gpio.h> 49261413Sbr 50281092Sandrew#include <vm/vm.h> 51281092Sandrew#include <vm/pmap.h> 52281092Sandrew 53261413Sbr#include <dev/ofw/openfirm.h> 54261413Sbr#include <dev/ofw/ofw_bus.h> 55261413Sbr#include <dev/ofw/ofw_bus_subr.h> 56261413Sbr 57261413Sbr#include <dev/vt/vt.h> 58261413Sbr#include <dev/vt/colors/vt_termcolors.h> 59261413Sbr 60262891Sbr#include "gpio_if.h" 61262891Sbr 62261413Sbr#include <machine/bus.h> 63261413Sbr#include <machine/fdt.h> 64261413Sbr#include <machine/cpu.h> 65261413Sbr#include <machine/intr.h> 66261413Sbr 67261413Sbr#include "fb_if.h" 68261413Sbr 69261413Sbr#include <arm/freescale/vybrid/vf_common.h> 70261413Sbr 71261413Sbr#define DCU_CTRLDESCCURSOR1 0x000 /* Control Descriptor Cursor 1 */ 72261413Sbr#define DCU_CTRLDESCCURSOR2 0x004 /* Control Descriptor Cursor 2 */ 73261413Sbr#define DCU_CTRLDESCCURSOR3 0x008 /* Control Descriptor Cursor 3 */ 74261413Sbr#define DCU_CTRLDESCCURSOR4 0x00C /* Control Descriptor Cursor 4 */ 75261413Sbr#define DCU_DCU_MODE 0x010 /* DCU4 Mode */ 76261413Sbr#define DCU_MODE_M 0x3 77261413Sbr#define DCU_MODE_S 0 78261413Sbr#define DCU_MODE_NORMAL 0x1 79261413Sbr#define DCU_MODE_TEST 0x2 80261413Sbr#define DCU_MODE_COLBAR 0x3 81261413Sbr#define RASTER_EN (1 << 14) /* Raster scan of pixel data */ 82262891Sbr#define PDI_EN (1 << 13) 83262891Sbr#define PDI_DE_MODE (1 << 11) 84262891Sbr#define PDI_MODE_M 2 85261413Sbr#define DCU_BGND 0x014 /* Background */ 86261413Sbr#define DCU_DISP_SIZE 0x018 /* Display Size */ 87261413Sbr#define DELTA_M 0x7ff 88261413Sbr#define DELTA_Y_S 16 89261413Sbr#define DELTA_X_S 0 90261413Sbr#define DCU_HSYN_PARA 0x01C /* Horizontal Sync Parameter */ 91261413Sbr#define BP_H_SHIFT 22 92261413Sbr#define PW_H_SHIFT 11 93261413Sbr#define FP_H_SHIFT 0 94261413Sbr#define DCU_VSYN_PARA 0x020 /* Vertical Sync Parameter */ 95261413Sbr#define BP_V_SHIFT 22 96261413Sbr#define PW_V_SHIFT 11 97261413Sbr#define FP_V_SHIFT 0 98261413Sbr#define DCU_SYNPOL 0x024 /* Synchronize Polarity */ 99261413Sbr#define INV_HS (1 << 0) 100261413Sbr#define INV_VS (1 << 1) 101262891Sbr#define INV_PDI_VS (1 << 8) /* Polarity of PDI input VSYNC. */ 102262891Sbr#define INV_PDI_HS (1 << 9) /* Polarity of PDI input HSYNC. */ 103262891Sbr#define INV_PDI_DE (1 << 10) /* Polarity of PDI input DE. */ 104261413Sbr#define DCU_THRESHOLD 0x028 /* Threshold */ 105261413Sbr#define LS_BF_VS_SHIFT 16 106261413Sbr#define OUT_BUF_HIGH_SHIFT 8 107261413Sbr#define OUT_BUF_LOW_SHIFT 0 108261413Sbr#define DCU_INT_STATUS 0x02C /* Interrupt Status */ 109261413Sbr#define DCU_INT_MASK 0x030 /* Interrupt Mask */ 110261413Sbr#define DCU_COLBAR_1 0x034 /* COLBAR_1 */ 111261413Sbr#define DCU_COLBAR_2 0x038 /* COLBAR_2 */ 112261413Sbr#define DCU_COLBAR_3 0x03C /* COLBAR_3 */ 113261413Sbr#define DCU_COLBAR_4 0x040 /* COLBAR_4 */ 114261413Sbr#define DCU_COLBAR_5 0x044 /* COLBAR_5 */ 115261413Sbr#define DCU_COLBAR_6 0x048 /* COLBAR_6 */ 116261413Sbr#define DCU_COLBAR_7 0x04C /* COLBAR_7 */ 117261413Sbr#define DCU_COLBAR_8 0x050 /* COLBAR_8 */ 118261413Sbr#define DCU_DIV_RATIO 0x054 /* Divide Ratio */ 119261413Sbr#define DCU_SIGN_CALC_1 0x058 /* Sign Calculation 1 */ 120261413Sbr#define DCU_SIGN_CALC_2 0x05C /* Sign Calculation 2 */ 121261413Sbr#define DCU_CRC_VAL 0x060 /* CRC Value */ 122261413Sbr#define DCU_PDI_STATUS 0x064 /* PDI Status */ 123261413Sbr#define DCU_PDI_STA_MSK 0x068 /* PDI Status Mask */ 124261413Sbr#define DCU_PARR_ERR_STATUS1 0x06C /* Parameter Error Status 1 */ 125261413Sbr#define DCU_PARR_ERR_STATUS2 0x070 /* Parameter Error Status 2 */ 126261413Sbr#define DCU_PARR_ERR_STATUS3 0x07C /* Parameter Error Status 3 */ 127261413Sbr#define DCU_MASK_PARR_ERR_ST1 0x080 /* Mask Parameter Error Status 1 */ 128261413Sbr#define DCU_MASK_PARR_ERR_ST2 0x084 /* Mask Parameter Error Status 2 */ 129261413Sbr#define DCU_MASK_PARR_ERR_ST3 0x090 /* Mask Parameter Error Status 3 */ 130261413Sbr#define DCU_THRESHOLD_INP_BUF_1 0x094 /* Threshold Input 1 */ 131261413Sbr#define DCU_THRESHOLD_INP_BUF_2 0x098 /* Threshold Input 2 */ 132261413Sbr#define DCU_THRESHOLD_INP_BUF_3 0x09C /* Threshold Input 3 */ 133261413Sbr#define DCU_LUMA_COMP 0x0A0 /* LUMA Component */ 134261413Sbr#define DCU_CHROMA_RED 0x0A4 /* Red Chroma Components */ 135261413Sbr#define DCU_CHROMA_GREEN 0x0A8 /* Green Chroma Components */ 136261413Sbr#define DCU_CHROMA_BLUE 0x0AC /* Blue Chroma Components */ 137261413Sbr#define DCU_CRC_POS 0x0B0 /* CRC Position */ 138261413Sbr#define DCU_LYR_INTPOL_EN 0x0B4 /* Layer Interpolation Enable */ 139261413Sbr#define DCU_LYR_LUMA_COMP 0x0B8 /* Layer Luminance Component */ 140261413Sbr#define DCU_LYR_CHRM_RED 0x0BC /* Layer Chroma Red */ 141261413Sbr#define DCU_LYR_CHRM_GRN 0x0C0 /* Layer Chroma Green */ 142261413Sbr#define DCU_LYR_CHRM_BLUE 0x0C4 /* Layer Chroma Blue */ 143261413Sbr#define DCU_COMP_IMSIZE 0x0C8 /* Compression Image Size */ 144261413Sbr#define DCU_UPDATE_MODE 0x0CC /* Update Mode */ 145261413Sbr#define READREG (1 << 30) 146261413Sbr#define MODE (1 << 31) 147261413Sbr#define DCU_UNDERRUN 0x0D0 /* Underrun */ 148261413Sbr#define DCU_GLBL_PROTECT 0x100 /* Global Protection */ 149261413Sbr#define DCU_SFT_LCK_BIT_L0 0x104 /* Soft Lock Bit Layer 0 */ 150261413Sbr#define DCU_SFT_LCK_BIT_L1 0x108 /* Soft Lock Bit Layer 1 */ 151261413Sbr#define DCU_SFT_LCK_DISP_SIZE 0x10C /* Soft Lock Display Size */ 152261413Sbr#define DCU_SFT_LCK_HS_VS_PARA 0x110 /* Soft Lock Hsync/Vsync Parameter */ 153261413Sbr#define DCU_SFT_LCK_POL 0x114 /* Soft Lock POL */ 154261413Sbr#define DCU_SFT_LCK_L0_TRANSP 0x118 /* Soft Lock L0 Transparency */ 155261413Sbr#define DCU_SFT_LCK_L1_TRANSP 0x11C /* Soft Lock L1 Transparency */ 156261413Sbr 157261413Sbr/* Control Descriptor */ 158261413Sbr#define DCU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1) 159261413Sbr#define DCU_CTRLDESCLn_1(n) DCU_CTRLDESCL(n, 1) 160261413Sbr#define DCU_CTRLDESCLn_2(n) DCU_CTRLDESCL(n, 2) 161261413Sbr#define DCU_CTRLDESCLn_3(n) DCU_CTRLDESCL(n, 3) 162261413Sbr#define TRANS_SHIFT 20 163261413Sbr#define DCU_CTRLDESCLn_4(n) DCU_CTRLDESCL(n, 4) 164261413Sbr#define BPP_MASK 0xf /* Bit per pixel Mask */ 165261413Sbr#define BPP_SHIFT 16 /* Bit per pixel Shift */ 166261413Sbr#define BPP24 0x5 167261413Sbr#define EN_LAYER (1 << 31) /* Enable the layer */ 168261413Sbr#define DCU_CTRLDESCLn_5(n) DCU_CTRLDESCL(n, 5) 169261413Sbr#define DCU_CTRLDESCLn_6(n) DCU_CTRLDESCL(n, 6) 170261413Sbr#define DCU_CTRLDESCLn_7(n) DCU_CTRLDESCL(n, 7) 171261413Sbr#define DCU_CTRLDESCLn_8(n) DCU_CTRLDESCL(n, 8) 172261413Sbr#define DCU_CTRLDESCLn_9(n) DCU_CTRLDESCL(n, 9) 173261413Sbr 174262891Sbr#define NUM_LAYERS 64 175261413Sbr 176262891Sbrstruct panel_info { 177262891Sbr uint32_t width; 178262891Sbr uint32_t height; 179262891Sbr uint32_t h_back_porch; 180262891Sbr uint32_t h_pulse_width; 181262891Sbr uint32_t h_front_porch; 182262891Sbr uint32_t v_back_porch; 183262891Sbr uint32_t v_pulse_width; 184262891Sbr uint32_t v_front_porch; 185262891Sbr uint32_t clk_div; 186262891Sbr uint32_t backlight_pin; 187262891Sbr}; 188262891Sbr 189261413Sbrstruct dcu_softc { 190261413Sbr struct resource *res[2]; 191261413Sbr bus_space_tag_t bst; 192261413Sbr bus_space_handle_t bsh; 193261413Sbr void *ih; 194261413Sbr device_t dev; 195261413Sbr device_t sc_fbd; /* fbd child */ 196261413Sbr struct fb_info sc_info; 197262891Sbr struct panel_info *panel; 198261413Sbr}; 199261413Sbr 200261413Sbrstatic struct resource_spec dcu_spec[] = { 201261413Sbr { SYS_RES_MEMORY, 0, RF_ACTIVE }, 202261413Sbr { SYS_RES_IRQ, 0, RF_ACTIVE }, 203261413Sbr { -1, 0 } 204261413Sbr}; 205261413Sbr 206261413Sbrstatic int 207261413Sbrdcu_probe(device_t dev) 208261413Sbr{ 209261413Sbr 210261413Sbr if (!ofw_bus_status_okay(dev)) 211261413Sbr return (ENXIO); 212261413Sbr 213261413Sbr if (!ofw_bus_is_compatible(dev, "fsl,mvf600-dcu4")) 214261413Sbr return (ENXIO); 215261413Sbr 216261413Sbr device_set_desc(dev, "Vybrid Family Display Control Unit (DCU4)"); 217261413Sbr return (BUS_PROBE_DEFAULT); 218261413Sbr} 219261413Sbr 220261413Sbrstatic void 221261413Sbrdcu_intr(void *arg) 222261413Sbr{ 223261413Sbr struct dcu_softc *sc; 224261413Sbr int reg; 225261413Sbr 226261413Sbr sc = arg; 227261413Sbr 228261413Sbr /* Ack interrupts */ 229261413Sbr reg = READ4(sc, DCU_INT_STATUS); 230261413Sbr WRITE4(sc, DCU_INT_STATUS, reg); 231261413Sbr 232261413Sbr /* TODO interrupt handler */ 233261413Sbr} 234261413Sbr 235261413Sbrstatic int 236262891Sbrget_panel_info(struct dcu_softc *sc, struct panel_info *panel) 237262891Sbr{ 238262891Sbr phandle_t node; 239262891Sbr pcell_t dts_value[3]; 240262891Sbr int len; 241262891Sbr 242262891Sbr if ((node = ofw_bus_get_node(sc->dev)) == -1) 243262891Sbr return (ENXIO); 244262891Sbr 245262891Sbr /* panel size */ 246262891Sbr if ((len = OF_getproplen(node, "panel-size")) <= 0) 247262891Sbr return (ENXIO); 248314503Sian OF_getencprop(node, "panel-size", dts_value, len); 249314503Sian panel->width = dts_value[0]; 250314503Sian panel->height = dts_value[1]; 251262891Sbr 252262891Sbr /* hsync */ 253262891Sbr if ((len = OF_getproplen(node, "panel-hsync")) <= 0) 254262891Sbr return (ENXIO); 255314503Sian OF_getencprop(node, "panel-hsync", dts_value, len); 256314503Sian panel->h_back_porch = dts_value[0]; 257314503Sian panel->h_pulse_width = dts_value[1]; 258314503Sian panel->h_front_porch = dts_value[2]; 259262891Sbr 260262891Sbr /* vsync */ 261262891Sbr if ((len = OF_getproplen(node, "panel-vsync")) <= 0) 262262891Sbr return (ENXIO); 263314503Sian OF_getencprop(node, "panel-vsync", dts_value, len); 264314503Sian panel->v_back_porch = dts_value[0]; 265314503Sian panel->v_pulse_width = dts_value[1]; 266314503Sian panel->v_front_porch = dts_value[2]; 267262891Sbr 268262891Sbr /* clk divider */ 269262891Sbr if ((len = OF_getproplen(node, "panel-clk-div")) <= 0) 270262891Sbr return (ENXIO); 271314503Sian OF_getencprop(node, "panel-clk-div", dts_value, len); 272314503Sian panel->clk_div = dts_value[0]; 273262891Sbr 274262891Sbr /* backlight pin */ 275262891Sbr if ((len = OF_getproplen(node, "panel-backlight-pin")) <= 0) 276262891Sbr return (ENXIO); 277314503Sian OF_getencprop(node, "panel-backlight-pin", dts_value, len); 278314503Sian panel->backlight_pin = dts_value[0]; 279262891Sbr 280262891Sbr return (0); 281262891Sbr} 282262891Sbr 283262891Sbrstatic int 284261413Sbrdcu_init(struct dcu_softc *sc) 285261413Sbr{ 286262891Sbr struct panel_info *panel; 287261413Sbr int reg; 288262891Sbr int i; 289261413Sbr 290262891Sbr panel = sc->panel; 291262891Sbr 292261413Sbr /* Configure DCU */ 293261413Sbr reg = ((sc->sc_info.fb_height) << DELTA_Y_S); 294261413Sbr reg |= (sc->sc_info.fb_width / 16); 295261413Sbr WRITE4(sc, DCU_DISP_SIZE, reg); 296261413Sbr 297262891Sbr reg = (panel->h_back_porch << BP_H_SHIFT); 298262891Sbr reg |= (panel->h_pulse_width << PW_H_SHIFT); 299262891Sbr reg |= (panel->h_front_porch << FP_H_SHIFT); 300261413Sbr WRITE4(sc, DCU_HSYN_PARA, reg); 301261413Sbr 302262891Sbr reg = (panel->v_back_porch << BP_V_SHIFT); 303262891Sbr reg |= (panel->v_pulse_width << PW_V_SHIFT); 304262891Sbr reg |= (panel->v_front_porch << FP_V_SHIFT); 305261413Sbr WRITE4(sc, DCU_VSYN_PARA, reg); 306261413Sbr 307261413Sbr WRITE4(sc, DCU_BGND, 0); 308262891Sbr WRITE4(sc, DCU_DIV_RATIO, panel->clk_div); 309261413Sbr 310261413Sbr reg = (INV_VS | INV_HS); 311261413Sbr WRITE4(sc, DCU_SYNPOL, reg); 312261413Sbr 313262891Sbr /* TODO: export to panel info */ 314261413Sbr reg = (0x3 << LS_BF_VS_SHIFT); 315261413Sbr reg |= (0x78 << OUT_BUF_HIGH_SHIFT); 316261413Sbr reg |= (0 << OUT_BUF_LOW_SHIFT); 317261413Sbr WRITE4(sc, DCU_THRESHOLD, reg); 318261413Sbr 319261413Sbr /* Mask all the interrupts */ 320261413Sbr WRITE4(sc, DCU_INT_MASK, 0xffffffff); 321261413Sbr 322262891Sbr /* Reset all layers */ 323262891Sbr for (i = 0; i < NUM_LAYERS; i++) { 324262891Sbr WRITE4(sc, DCU_CTRLDESCLn_1(i), 0x0); 325262891Sbr WRITE4(sc, DCU_CTRLDESCLn_2(i), 0x0); 326262891Sbr WRITE4(sc, DCU_CTRLDESCLn_3(i), 0x0); 327262891Sbr WRITE4(sc, DCU_CTRLDESCLn_4(i), 0x0); 328262891Sbr WRITE4(sc, DCU_CTRLDESCLn_5(i), 0x0); 329262891Sbr WRITE4(sc, DCU_CTRLDESCLn_6(i), 0x0); 330262891Sbr WRITE4(sc, DCU_CTRLDESCLn_7(i), 0x0); 331262891Sbr WRITE4(sc, DCU_CTRLDESCLn_8(i), 0x0); 332262891Sbr WRITE4(sc, DCU_CTRLDESCLn_9(i), 0x0); 333262891Sbr } 334262891Sbr 335261413Sbr /* Setup first layer */ 336261413Sbr reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16)); 337261413Sbr WRITE4(sc, DCU_CTRLDESCLn_1(0), reg); 338261413Sbr WRITE4(sc, DCU_CTRLDESCLn_2(0), 0x0); 339261413Sbr WRITE4(sc, DCU_CTRLDESCLn_3(0), sc->sc_info.fb_pbase); 340261413Sbr reg = (BPP24 << BPP_SHIFT); 341261413Sbr reg |= EN_LAYER; 342261413Sbr reg |= (0xFF << TRANS_SHIFT); /* completely opaque */ 343261413Sbr WRITE4(sc, DCU_CTRLDESCLn_4(0), reg); 344261413Sbr WRITE4(sc, DCU_CTRLDESCLn_5(0), 0xffffff); 345261413Sbr WRITE4(sc, DCU_CTRLDESCLn_6(0), 0x0); 346261413Sbr WRITE4(sc, DCU_CTRLDESCLn_7(0), 0x0); 347261413Sbr WRITE4(sc, DCU_CTRLDESCLn_8(0), 0x0); 348261413Sbr WRITE4(sc, DCU_CTRLDESCLn_9(0), 0x0); 349261413Sbr 350261413Sbr /* Enable DCU in normal mode */ 351261413Sbr reg = READ4(sc, DCU_DCU_MODE); 352261413Sbr reg &= ~(DCU_MODE_M << DCU_MODE_S); 353261413Sbr reg |= (DCU_MODE_NORMAL << DCU_MODE_S); 354261413Sbr reg |= (RASTER_EN); 355261413Sbr WRITE4(sc, DCU_DCU_MODE, reg); 356261413Sbr WRITE4(sc, DCU_UPDATE_MODE, READREG); 357261413Sbr 358261413Sbr return (0); 359261413Sbr} 360261413Sbr 361261413Sbrstatic int 362261413Sbrdcu_attach(device_t dev) 363261413Sbr{ 364262891Sbr struct panel_info panel; 365261413Sbr struct dcu_softc *sc; 366262891Sbr device_t gpio_dev; 367261413Sbr int err; 368261413Sbr 369261413Sbr sc = device_get_softc(dev); 370262891Sbr sc->dev = dev; 371261413Sbr 372261413Sbr if (bus_alloc_resources(dev, dcu_spec, sc->res)) { 373261413Sbr device_printf(dev, "could not allocate resources\n"); 374261413Sbr return (ENXIO); 375261413Sbr } 376261413Sbr 377261413Sbr /* Memory interface */ 378261413Sbr sc->bst = rman_get_bustag(sc->res[0]); 379261413Sbr sc->bsh = rman_get_bushandle(sc->res[0]); 380261413Sbr 381261413Sbr /* Setup interrupt handler */ 382261413Sbr err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE, 383261413Sbr NULL, dcu_intr, sc, &sc->ih); 384261413Sbr if (err) { 385261413Sbr device_printf(dev, "Unable to alloc interrupt resource.\n"); 386261413Sbr return (ENXIO); 387261413Sbr } 388261413Sbr 389262891Sbr if (get_panel_info(sc, &panel)) { 390262891Sbr device_printf(dev, "Can't get panel info\n"); 391262891Sbr return (ENXIO); 392262891Sbr } 393262891Sbr 394262891Sbr sc->panel = &panel; 395262891Sbr 396261413Sbr /* Bypass timing control (used for raw lcd panels) */ 397261413Sbr tcon_bypass(); 398261413Sbr 399262891Sbr /* Get the GPIO device, we need this to give power to USB */ 400262891Sbr gpio_dev = devclass_get_device(devclass_find("gpio"), 0); 401262891Sbr if (gpio_dev == NULL) { 402262891Sbr device_printf(sc->dev, "Error: failed to get the GPIO dev\n"); 403262891Sbr return (1); 404262891Sbr } 405262891Sbr 406262891Sbr /* Turn on backlight */ 407262891Sbr /* TODO: Use FlexTimer/PWM */ 408262891Sbr GPIO_PIN_SETFLAGS(gpio_dev, panel.backlight_pin, GPIO_PIN_OUTPUT); 409262891Sbr GPIO_PIN_SET(gpio_dev, panel.backlight_pin, GPIO_PIN_HIGH); 410262891Sbr 411262891Sbr sc->sc_info.fb_width = panel.width; 412262891Sbr sc->sc_info.fb_height = panel.height; 413261413Sbr sc->sc_info.fb_stride = sc->sc_info.fb_width * 3; 414261413Sbr sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 24; 415261413Sbr sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride; 416261413Sbr sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size, 417261413Sbr M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0); 418261413Sbr sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase); 419261413Sbr 420261413Sbr#if 0 421261413Sbr printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height, 422261413Sbr sc->sc_info.fb_stride); 423261413Sbr printf("pbase == 0x%08x\n", sc->sc_info.fb_pbase); 424261413Sbr#endif 425261413Sbr 426261413Sbr memset((int8_t *)sc->sc_info.fb_vbase, 0x0, sc->sc_info.fb_size); 427261413Sbr 428261413Sbr dcu_init(sc); 429261413Sbr 430261413Sbr sc->sc_info.fb_name = device_get_nameunit(dev); 431261413Sbr 432261413Sbr /* Ask newbus to attach framebuffer device to me. */ 433261413Sbr sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev)); 434261413Sbr if (sc->sc_fbd == NULL) 435261413Sbr device_printf(dev, "Can't attach fbd device\n"); 436261413Sbr 437261413Sbr if (device_probe_and_attach(sc->sc_fbd) != 0) { 438261413Sbr device_printf(sc->dev, "Failed to attach fbd device\n"); 439261413Sbr } 440261413Sbr 441261413Sbr return (0); 442261413Sbr} 443261413Sbr 444261413Sbrstatic struct fb_info * 445261413Sbrdcu4_fb_getinfo(device_t dev) 446261413Sbr{ 447261413Sbr struct dcu_softc *sc = device_get_softc(dev); 448261413Sbr 449261413Sbr return (&sc->sc_info); 450261413Sbr} 451261413Sbr 452261413Sbrstatic device_method_t dcu_methods[] = { 453261413Sbr DEVMETHOD(device_probe, dcu_probe), 454261413Sbr DEVMETHOD(device_attach, dcu_attach), 455261413Sbr 456261413Sbr /* Framebuffer service methods */ 457261413Sbr DEVMETHOD(fb_getinfo, dcu4_fb_getinfo), 458261413Sbr { 0, 0 } 459261413Sbr}; 460261413Sbr 461261413Sbrstatic driver_t dcu_driver = { 462261413Sbr "fb", 463261413Sbr dcu_methods, 464261413Sbr sizeof(struct dcu_softc), 465261413Sbr}; 466261413Sbr 467261413Sbrstatic devclass_t dcu_devclass; 468261413Sbr 469261413SbrDRIVER_MODULE(fb, simplebus, dcu_driver, dcu_devclass, 0, 0); 470