Searched refs:UMC_BASE__INST5_SEG1 (Results 1 - 12 of 12) sorted by relevance

/linux-master/drivers/gpu/drm/amd/include/
H A Dnavi10_ip_offset.h807 #define UMC_BASE__INST5_SEG1 0 macro
H A Dvega20_ip_offset.h874 #define UMC_BASE__INST5_SEG1 0 macro
H A Dyellow_carp_offset.h1303 #define UMC_BASE__INST5_SEG1 0 macro
H A Drenoir_ip_offset.h1272 #define UMC_BASE__INST5_SEG1 0 macro
H A Dsienna_cichlid_ip_offset.h1071 #define UMC_BASE__INST5_SEG1 0x02426C00 macro
H A Dbeige_goby_ip_offset.h1210 #define UMC_BASE__INST5_SEG1 0 macro
H A Dnavi12_ip_offset.h1022 #define UMC_BASE__INST5_SEG1 0 macro
H A Dnavi14_ip_offset.h1022 #define UMC_BASE__INST5_SEG1 0 macro
H A Ddimgrey_cavefish_ip_offset.h985 #define UMC_BASE__INST5_SEG1 0 macro
H A Daldebaran_ip_offset.h1431 #define UMC_BASE__INST5_SEG1 0 macro
H A Dvangogh_ip_offset.h1382 #define UMC_BASE__INST5_SEG1 0 macro
H A Darct_ip_offset.h1459 #define UMC_BASE__INST5_SEG1 0x00154000 macro

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