| /linux-master/arch/x86/crypto/ |
| H A D | aesni-intel_avx-x86_64.S | 571 .macro CALC_AAD_HASH GHASH_MUL AAD AADLEN T1 T2 T3 T4 T5 T6 T7 T8
587 \GHASH_MUL \T8, \T2, \T1, \T3, \T4, \T5, \T6
635 \GHASH_MUL \T7, \T2, \T1, \T3, \T4, \T5, \T6
863 .macro GHASH_MUL_AVX GH HK T1 T2 T3 T4 T5
889 vpsrldq $4, \T2, \T5 # shift-R T5 1 DW
902 vpxor \T5, \T2, \T2
909 .macro PRECOMPUTE_AVX HK T1 T2 T3 T4 T5 T6
912 vmovdqa \HK, \T5
914 vpshufd $0b01001110, \T5, \T
[all...] |
| H A D | nh-avx2-x86_64.S | 32 #define T5 %ymm13 define
51 vpshufd $0x10, T1, T5
58 vpmuludq T5, T1, T1
149 vinserti128 $0x1, T3_XMM, T1, T5 // T5 = (0B 1B 2B 3B)
153 vpaddq T5, T4, T4
|
| H A D | nh-sse2-x86_64.S | 26 #define T5 %xmm13 define
53 pshufd $0x10, T1, T5
60 pmuludq T5, T1
|
| H A D | aesni-intel_asm.S | 1157 psrldq $4, \TMP5 # right shift T5 1 DW
1369 psrldq $4, \TMP5 # right shift T5 1 DW
|
| /linux-master/arch/arm64/crypto/ |
| H A D | nh-neon-core.S | 31 T5 .req v13
51 mov T5.d[0], T1.d[1]
55 umlal PASS1_SUMS.2d, T1.2s, T5.2s
|
| H A D | sha512-armv8.pl | 463 my ($T0,$T1,$T2,$T3,$T4,$T5,$T6,$T7) = map("q$_",(4..7,16..19));
520 &ushr_32 ($T5,$T7,$sigma1[2]);
532 &eor_8 ($T5,$T5,$T4);
536 &eor_8 ($T5,$T5,$T3); # sigma1(X[14..15])
540 &add_32 (@X[0],@X[0],$T5); # X[0..1] += sigma1(X[14..15])
551 &ushr_32 ($T5,@X[0],$sigma1[1]);
557 &sli_32 ($T5,@X[0],32-$sigma1[1]);
562 &eor_8 ($T7,$T7,$T5); # sigma
[all...] |
| H A D | sm4-ce-gcm-core.S | 53 r4, r5, m4, m5, T4, T5, \
65 pmull T5.1q, m4.1d, T4.1d; \
77 eor T4.16b, T4.16b, T5.16b; \
81 ext T5.16b, RZERO.16b, T4.16b, #8; \
89 eor r4.16b, r4.16b, T5.16b; \
136 r4, r5, m4, m5, T4, T5) \
154 pmull T5.1q, m4.1d, T4.1d; \
172 eor T4.16b, T4.16b, T5.16b; \
178 ext T5.16b, RZERO.16b, T4.16b, #8; \
190 eor r4.16b, r4.16b, T5
[all...] |
| /linux-master/crypto/ |
| H A D | anubis.c | 387 static const u32 T5[256] = { variable
501 (T5[(K0 >> 24) ] & 0xff000000U) ^
502 (T5[(K0 >> 16) & 0xff] & 0x00ff0000U) ^
503 (T5[(K0 >> 8) & 0xff] & 0x0000ff00U) ^
504 (T5[(K0 ) & 0xff] & 0x000000ffU);
506 (T5[(K1 >> 24) ] & 0xff000000U) ^
507 (T5[(K1 >> 16) & 0xff] & 0x00ff0000U) ^
508 (T5[(K1 >> 8) & 0xff] & 0x0000ff00U) ^
509 (T5[(K1 ) & 0xff] & 0x000000ffU);
511 (T5[(K
[all...] |
| H A D | khazad.c | 483 static const u64 T5[256] = { variable
776 T5[(int)(K1 >> 16) & 0xff] ^
792 T5[(int)S[(int)(K1 >> 16) & 0xff] & 0xff] ^
818 T5[(int)(state >> 16) & 0xff] ^
829 (T5[(int)(state >> 16) & 0xff] & 0x0000000000ff0000ULL) ^
|
| /linux-master/arch/arm/crypto/ |
| H A D | sha256-armv4.pl | 292 my ($T0,$T1,$T2,$T3,$T4,$T5)=("q8","q9","q10","q11","d24","d25");
350 &vshr_u32 ($T5,&Dhi(@X[3]),$sigma1[2]);
356 &veor ($T5,$T5,$T4);
365 &veor ($T5,$T5,$T4); # sigma1(X[14..15])
368 &vadd_i32 (&Dlo(@X[0]),&Dlo(@X[0]),$T5);# X[0..1] += sigma1(X[14..15])
377 &vshr_u32 ($T5,&Dlo(@X[0]),$sigma1[2]);
380 &veor ($T5,$T5,
[all...] |
| /linux-master/tools/perf/arch/riscv/util/ |
| H A D | unwind-libdw.c | 52 dwarf_regs[30] = REG(T5);
|
| /linux-master/drivers/pinctrl/aspeed/ |
| H A D | pinctrl-aspeed-g4.c | 694 #define T5 89 macro
703 SIG_EXPR_LIST_ALIAS(T5, VPIDE, VPI);
704 SIG_EXPR_LIST_DECL_SINGLE(T5, NDCD1, NDCD1, T5_DESC);
705 PIN_DECL_2(T5, GPIOL1, VPIDE, NDCD1);
706 FUNC_GROUP_DECL(NDCD1, T5);
1032 FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5,
1034 FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5,
1037 FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, V3, W2, Y1, V4, W3, Y2, AA1,
2090 ASPEED_PINCTRL_PIN(T5),
|
| H A D | pinctrl-aspeed-g5.c | 798 #define T5 103 macro
800 SIG_EXPR_LIST_DECL_SINGLE(T5, VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2);
801 SIG_EXPR_LIST_DECL_SINGLE(T5, RXD2, RXD2, T5_DESC, COND2);
802 PIN_DECL_2(T5, GPIOM7, VPIB9, RXD2);
803 FUNC_GROUP_DECL(RXD2, T5);
929 FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3,
2095 ASPEED_PINCTRL_PIN(T5),
2535 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, T5, SCU8C, 28),
2536 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, T5, SCU8C, 28),
|
| /linux-master/drivers/scsi/csiostor/ |
| H A D | csio_hw.c | 2280 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
2281 .intfver_nic = FW_INTFVER(T5, NIC),
2282 .intfver_vnic = FW_INTFVER(T5, VNIC),
2283 .intfver_ri = FW_INTFVER(T5, RI),
2284 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2285 .intfver_fcoe = FW_INTFVER(T5, FCOE),
4356 /* Initialize the HW chip ops T5 specific ops */
|
| /linux-master/drivers/net/ethernet/chelsio/cxgb4/ |
| H A D | cxgb4_main.c | 95 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
1895 /* Reserve stid 0 for T4/T5 adapters */
4720 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
4721 .intfver_nic = FW_INTFVER(T5, NIC),
4722 .intfver_vnic = FW_INTFVER(T5, VNIC),
4723 .intfver_ri = FW_INTFVER(T5, RI),
4724 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
4725 .intfver_fcoe = FW_INTFVER(T5, FCOE),
5113 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
|