/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
H A D | dcn35_hubbub.h | 33 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ 34 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ 35 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ 36 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ 37 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ 38 SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ 39 SR(DCHUBBUB_ARB_SAT_LEVEL),\ 40 SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ 41 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 42 SR(DCHUBBUB_SOFT_RESE [all...] |
H A D | dcn35_pg_cntl.h | 33 SR(DOMAIN0_PG_CONFIG), \ 34 SR(DOMAIN1_PG_CONFIG), \ 35 SR(DOMAIN2_PG_CONFIG), \ 36 SR(DOMAIN3_PG_CONFIG), \ 37 SR(DOMAIN16_PG_CONFIG), \ 38 SR(DOMAIN17_PG_CONFIG), \ 39 SR(DOMAIN18_PG_CONFIG), \ 40 SR(DOMAIN19_PG_CONFIG), \ 41 SR(DOMAIN22_PG_CONFIG), \ 42 SR(DOMAIN23_PG_CONFI [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
H A D | dce_dmcu.h | 33 SR(DMCU_CTRL), \ 34 SR(DMCU_STATUS), \ 35 SR(DMCU_RAM_ACCESS_CTRL), \ 36 SR(DMCU_IRAM_WR_CTRL), \ 37 SR(DMCU_IRAM_WR_DATA), \ 38 SR(MASTER_COMM_DATA_REG1), \ 39 SR(MASTER_COMM_DATA_REG2), \ 40 SR(MASTER_COMM_DATA_REG3), \ 41 SR(MASTER_COMM_CMD_REG), \ 42 SR(MASTER_COMM_CNTL_RE [all...] |
H A D | dce_abm.h | 33 SR(MASTER_COMM_CNTL_REG), \ 34 SR(MASTER_COMM_CMD_REG), \ 35 SR(MASTER_COMM_DATA_REG1) 39 SR(DC_ABM1_HG_SAMPLE_RATE), \ 40 SR(DC_ABM1_LS_SAMPLE_RATE), \ 41 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ 42 SR(DC_ABM1_HG_MISC_CTRL), \ 43 SR(DC_ABM1_IPCSC_COEFF_SEL), \ 44 SR(BL1_PWM_CURRENT_ABM_LEVEL), \ 45 SR(BL1_PWM_TARGET_ABM_LEVE [all...] |
H A D | dce_panel_cntl.h | 39 SR(BL_PWM_CNTL), \ 40 SR(BL_PWM_CNTL2), \ 41 SR(BL_PWM_PERIOD_CNTL), \ 42 SR(BL_PWM_GRP1_REG_LOCK), \ 43 SR(BIOS_SCRATCH_2) 53 SR(BL_PWM_CNTL), \ 54 SR(BL_PWM_CNTL2), \ 55 SR(BL_PWM_PERIOD_CNTL), \ 56 SR(BL_PWM_GRP1_REG_LOCK), \
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H A D | dce_audio.h | 33 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\ 34 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\ 35 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\ 36 SR(DCCG_AUDIO_DTO_SOURCE),\ 37 SR(DCCG_AUDIO_DTO0_MODULE),\ 38 SR(DCCG_AUDIO_DTO0_PHASE),\ 39 SR(DCCG_AUDIO_DTO1_MODULE),\ 40 SR(DCCG_AUDIO_DTO1_PHASE)
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H A D | dce_link_encoder.h | 48 SR(DMCU_RAM_ACCESS_CTRL), \ 49 SR(DMCU_IRAM_RD_CTRL), \ 50 SR(DMCU_IRAM_RD_DATA), \ 51 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 77 SR(DCI_MEM_PWR_STATUS) 82 SR(DMCU_RAM_ACCESS_CTRL), \ 83 SR(DMCU_IRAM_RD_CTRL), \ 84 SR(DMCU_IRAM_RD_DATA), \ 85 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 115 SR(DCI_MEM_PWR_STATU [all...] |
H A D | dce_i2c_hw.h | 88 SR(DC_I2C_ARBITRATION),\ 89 SR(DC_I2C_CONTROL),\ 90 SR(DC_I2C_SW_STATUS),\ 91 SR(DC_I2C_TRANSACTION0),\ 92 SR(DC_I2C_TRANSACTION1),\ 93 SR(DC_I2C_TRANSACTION2),\ 94 SR(DC_I2C_TRANSACTION3),\ 95 SR(DC_I2C_DATA),\ 96 SR(MICROSECOND_TIME_BASE_DIV) 100 SR(DIO_MEM_PWR_CTR [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce/ |
H A D | dce_hwseq.h | 45 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 129 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 130 SR(DCFEV_CLOCK_CONTROL), \ 139 SR(BLNDV_CONTROL),\ 180 SR(DCHUB_FB_LOCATION),\ 181 SR(DCHUB_AGP_BASE),\ 182 SR(DCHUB_AGP_BOT),\ 183 SR(DCHUB_AGP_TOP) 195 SR(REFCLK_CNTL), \ 196 SR(DCHUBBUB_GLOBAL_TIMER_CNT [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/ |
H A D | dcn20_hubbub.h | 37 SR(DCHUBBUB_CRC_CTRL), \ 38 SR(DCN_VM_FB_LOCATION_BASE),\ 39 SR(DCN_VM_FB_LOCATION_TOP),\ 40 SR(DCN_VM_FB_OFFSET),\ 41 SR(DCN_VM_AGP_BOT),\ 42 SR(DCN_VM_AGP_TOP),\ 43 SR(DCN_VM_AGP_BASE),\ 44 SR(DCN_VM_FAULT_ADDR_MSB), \ 45 SR(DCN_VM_FAULT_ADDR_LSB), \ 46 SR(DCN_VM_FAULT_CNT [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
H A D | dcn35_resource.h | 162 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 163 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 164 SR(DIO_MEM_PWR_CTRL), \ 165 SR(ODM_MEM_PWR_CTRL3), \ 166 SR(MMHUBBUB_MEM_PWR_CNTL), \ 167 SR(DCCG_GATE_DISABLE_CNTL), \ 168 SR(DCCG_GATE_DISABLE_CNTL2), \ 169 SR(DCCG_GATE_DISABLE_CNTL4), \ 170 SR(DCCG_GATE_DISABLE_CNTL5), \ 171 SR(DCFCLK_CNT [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/ |
H A D | dcn30_dccg.h | 34 SR(PHYASYMCLK_CLOCK_CNTL),\ 35 SR(PHYBSYMCLK_CLOCK_CNTL),\ 36 SR(PHYCSYMCLK_CLOCK_CNTL) 45 SR(PHYASYMCLK_CLOCK_CNTL),\ 46 SR(PHYBSYMCLK_CLOCK_CNTL),\ 47 SR(PHYCSYMCLK_CLOCK_CNTL)
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H A D | dcn30_dwb.h | 31 SR(DWB_ENABLE_CLK_CTRL),\ 32 SR(DWB_MEM_PWR_CTRL),\ 33 SR(FC_MODE_CTRL),\ 34 SR(FC_FLOW_CTRL),\ 35 SR(FC_WINDOW_START),\ 36 SR(FC_WINDOW_SIZE),\ 37 SR(FC_SOURCE_SIZE),\ 38 SR(DWB_UPDATE_CTRL),\ 39 SR(DWB_CRC_CTRL),\ 40 SR(DWB_CRC_MASK_R_ [all...] |
H A D | dcn30_hubbub.h | 40 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ 41 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ 42 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ 43 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ 44 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ 45 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ 46 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ 47 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ 48 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\ 49 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_ [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/ |
H A D | dcn31_hubbub.h | 33 SR(DCHVM_CTRL0),\ 34 SR(DCHVM_MEM_CTRL),\ 35 SR(DCHVM_CLK_CTRL),\ 36 SR(DCHVM_RIOMMU_CTRL0),\ 37 SR(DCHVM_RIOMMU_STAT0),\ 38 SR(DCHUBBUB_DET0_CTRL),\ 39 SR(DCHUBBUB_DET1_CTRL),\ 40 SR(DCHUBBUB_DET2_CTRL),\ 41 SR(DCHUBBUB_DET3_CTRL),\ 42 SR(DCHUBBUB_COMPBUF_CTR [all...] |
H A D | dcn31_dccg.h | 32 SR(DPPCLK_DTO_CTRL),\ 37 SR(PHYASYMCLK_CLOCK_CNTL),\ 38 SR(PHYBSYMCLK_CLOCK_CNTL),\ 39 SR(PHYCSYMCLK_CLOCK_CNTL),\ 40 SR(PHYDSYMCLK_CLOCK_CNTL),\ 41 SR(PHYESYMCLK_CLOCK_CNTL),\ 42 SR(DPSTREAMCLK_CNTL),\ 43 SR(SYMCLK32_SE_CNTL),\ 44 SR(SYMCLK32_LE_CNTL),\ 57 SR(DCCG_AUDIO_DTBCLK_DTO_MODUL [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn314/ |
H A D | dcn314_dccg.h | 37 SR(DPPCLK_DTO_CTRL),\ 43 SR(PHYASYMCLK_CLOCK_CNTL),\ 44 SR(PHYBSYMCLK_CLOCK_CNTL),\ 45 SR(PHYCSYMCLK_CLOCK_CNTL),\ 46 SR(PHYDSYMCLK_CLOCK_CNTL),\ 47 SR(PHYESYMCLK_CLOCK_CNTL),\ 48 SR(DPSTREAMCLK_CNTL),\ 49 SR(HDMISTREAMCLK_CNTL),\ 50 SR(SYMCLK32_SE_CNTL),\ 51 SR(SYMCLK32_LE_CNT [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
H A D | dcn10_hubbub.h | 36 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ 37 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\ 38 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ 39 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\ 40 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ 41 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\ 42 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ 43 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\ 44 SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ 45 SR(DCHUBBUB_ARB_DRAM_STATE_CNT [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn21/ |
H A D | dcn21_hubbub.h | 31 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ 32 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ 33 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ 34 SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ 35 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ 36 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ 37 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ 38 SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ 39 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\ 40 SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_ [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/ |
H A D | dcn201_hubbub.h | 33 SR(DCHUBBUB_CRC_CTRL)
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn303/ |
H A D | dcn303_dccg.h | 33 SR(DPPCLK_DTO_CTRL),\ 36 SR(REFCLK_CNTL),\ 37 SR(DISPCLK_FREQ_CHANGE_CNTL),\
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/linux-master/drivers/video/fbdev/via/ |
H A D | viamode.h | 15 unsigned char SR[StdSR]; member in struct:VPITTable
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn301/ |
H A D | dcn301_dccg.h | 32 SR(DPPCLK_DTO_CTRL),\ 37 SR(REFCLK_CNTL)
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/linux-master/drivers/macintosh/ |
H A D | via-macii.c | 51 #define SR (10*RS) /* Shift register */ macro 178 x = via[SR]; 341 via[SR] = req->data[1]; 379 /* Clear the SR IRQ flag when polling. */ 400 x = via[SR]; 450 x = via[SR]; 463 x = via[SR]; 473 x = via[SR]; 489 via[SR] = req->data[data_index++]; 502 x = via[SR]; [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
H A D | dcn314_resource.c | 145 #define SR(reg_name)\ macro 686 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 687 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \ 688 SR(DIO_MEM_PWR_CTRL), \ 689 SR(ODM_MEM_PWR_CTRL3), \ 690 SR(DMU_MEM_PWR_CNTL), \ 691 SR(MMHUBBUB_MEM_PWR_CNTL), \ 692 SR(DCCG_GATE_DISABLE_CNTL), \ 693 SR(DCCG_GATE_DISABLE_CNTL2), \ 694 SR(DCFCLK_CNT [all...] |