Searched refs:SDMA0_BASE__INST5_SEG3 (Results 1 - 7 of 7) sorted by relevance

/linux-master/drivers/gpu/drm/amd/include/
H A Dvega20_ip_offset.h708 #define SDMA0_BASE__INST5_SEG3 0 macro
H A Dyellow_carp_offset.h1158 #define SDMA0_BASE__INST5_SEG3 0 macro
H A Drenoir_ip_offset.h1148 #define SDMA0_BASE__INST5_SEG3 0 macro
H A Dsienna_cichlid_ip_offset.h905 #define SDMA0_BASE__INST5_SEG3 0 macro
H A Dbeige_goby_ip_offset.h1065 #define SDMA0_BASE__INST5_SEG3 0 macro
H A Daldebaran_ip_offset.h1237 #define SDMA0_BASE__INST5_SEG3 0 macro
H A Darct_ip_offset.h954 #define SDMA0_BASE__INST5_SEG3 0 macro

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