Searched refs:RetVT (Results 1 - 19 of 19) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRuntimeLibcalls.h37 Libcall getFPEXT(EVT OpVT, EVT RetVT);
41 Libcall getFPROUND(EVT OpVT, EVT RetVT);
45 Libcall getFPTOSINT(EVT OpVT, EVT RetVT);
49 Libcall getFPTOUINT(EVT OpVT, EVT RetVT);
53 Libcall getSINTTOFP(EVT OpVT, EVT RetVT);
57 Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
H A DFastISel.h354 virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
358 virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
363 virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
369 virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
382 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
387 virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
446 unsigned fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill,
H A DTargetLowering.h3046 EVT RetVT, ArrayRef<SDValue> Ops,
3635 MakeLibCallOptions &setTypeListBeforeSoften(ArrayRef<EVT> OpsVT, EVT RetVT, argument
3638 RetVTBeforeSoften = RetVT;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp220 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { argument
222 if (RetVT == MVT::f32)
225 if (RetVT == MVT::f64)
227 if (RetVT == MVT::f128)
229 if (RetVT == MVT::ppcf128)
232 if (RetVT == MVT::f128)
234 else if (RetVT == MVT::ppcf128)
237 if (RetVT == MVT::f128)
246 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { argument
247 if (RetVT
284 getFPTOSINT(EVT OpVT, EVT RetVT) argument
326 getFPTOUINT(EVT OpVT, EVT RetVT) argument
368 getSINTTOFP(EVT OpVT, EVT RetVT) argument
408 getUINTTOFP(EVT OpVT, EVT RetVT) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp196 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
201 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
204 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
207 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
210 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
215 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
224 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
225 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
226 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
235 unsigned emitAdd(MVT RetVT, cons
1160 emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS, const Value *RHS, bool SetFlags, bool WantResult, bool IsZExt) argument
1314 emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, bool SetFlags, bool WantResult) argument
1352 emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm, bool SetFlags, bool WantResult) argument
1397 emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument
1440 emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ExtType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument
1507 emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt) argument
1513 emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm) argument
1519 emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) argument
1554 emitAdd(MVT RetVT, const Value *LHS, const Value *RHS, bool SetFlags, bool WantResult, bool IsZExt) argument
1584 emitSub(MVT RetVT, const Value *LHS, const Value *RHS, bool SetFlags, bool WantResult, bool IsZExt) argument
1590 emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, bool WantResult) argument
1597 emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool WantResult) argument
1607 emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS, const Value *RHS) argument
1691 emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm) argument
1737 emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, uint64_t ShiftImm) argument
1780 emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm) argument
1785 emitLoad(MVT VT, MVT RetVT, Address Addr, bool WantZExt, MachineMemOperand *MMO) argument
2008 MVT RetVT = VT; local
3152 finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes) argument
3399 MVT RetVT; local
3578 MVT RetVT; local
4046 emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
4066 emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
4076 emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
4086 emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument
4112 emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
4192 emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument
4219 emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
4313 emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, unsigned Op1Reg, bool Op1IsKill) argument
4340 emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool Op0IsKill, uint64_t Shift, bool IsZExt) argument
4531 optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT) argument
4588 MVT RetVT; local
4759 MVT RetVT; local
4848 MVT RetVT, SrcVT; local
4889 MVT RetVT; local
[all...]
H A DAArch64ISelLowering.cpp12431 EVT RetVT = N->getValueType(0); local
12432 assert(RetVT.isScalableVector() &&
12436 if (RetVT.getSizeInBits().getKnownMinSize() > AArch64::SVEBitsPerBlock)
12458 EVT HwRetVt = getSVEContainerType(RetVT);
12464 SDValue OutVT = DAG.getValueType(RetVT);
12465 if (RetVT.isFloatingPoint())
12476 if (RetVT.isInteger() && (RetVT != HwRetVt))
12477 Load = DAG.getNode(ISD::TRUNCATE, DL, RetVT, Load.getValue(0));
12481 if (RetVT
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DFastISelEmitter.cpp522 MVT::SimpleValueType RetVT = MVT::isVoid;
523 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getSimpleType(0);
524 MVT::SimpleValueType VT = RetVT;
596 [RetVT].count(PredicateCheck)) {
600 SimplePatternsCheck[Operands][OpcodeName][VT][RetVT].insert(
605 SimplePatterns[Operands][OpcodeName][VT][RetVT].emplace(complexity,
719 MVT::SimpleValueType RetVT = RI->first;
725 << "_" << getLegalCName(getName(RetVT)) << "_";
731 emitInstructionCode(OS, Operands, PM, getName(RetVT));
739 OS << "(MVT RetVT";
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp196 bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes);
1490 bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes) { argument
1501 if (RetVT != MVT::isVoid) {
1504 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1514 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1520 if (RetVT == CopyVT) {
1526 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1534 } else if (RetVT
1570 MVT RetVT; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp230 bool FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
2034 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs, argument
2044 if (RetVT != MVT::isVoid) {
2047 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2050 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2071 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2209 MVT RetVT; local
2211 RetVT
2315 MVT RetVT; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp121 bool X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I);
123 bool X86FastEmitSSESelect(MVT RetVT, const Instruction *I);
125 bool X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I);
248 MVT RetVT; local
252 if (!isTypeLegal(RetTy, RetVT))
255 if (RetVT != MVT::i32 && RetVT != MVT::i64)
2015 bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) { argument
2021 if (RetVT < MVT::i16 || RetVT > MV
2147 X86FastEmitSSESelect(MVT RetVT, const Instruction *I) argument
2282 X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) argument
2361 MVT RetVT; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp201 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
247 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
296 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT, argument
1279 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT, argument
1283 if (RetVT != MVT::isVoid) {
1297 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1515 MVT RetVT;
1517 RetVT
1963 MVT RetVT; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp2045 EVT RetVT = Node->getValueType(0);
2046 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2065 bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetVT, isSigned);
2105 EVT RetVT = Node->getValueType(0);
2109 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
2161 EVT RetVT = Node->getValueType(0);
2165 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
2199 EVT RetVT = Node->getValueType(0);
2200 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2215 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
[all...]
H A DLegalizeFloatTypes.cpp1882 EVT RetVT = N->getOperand(0).getValueType(); local
1884 return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
1895 EVT RetVT = N->getOperand(0).getValueType(); local
1897 return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
1908 EVT RetVT = N->getOperand(0).getValueType(); local
1910 return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
1921 EVT RetVT = N->getOperand(0).getValueType(); local
1923 return TLI.makeLibCall(DAG, GetFPLibCall(RetVT,
1937 static ISD::NodeType GetPromotionOpcode(EVT OpVT, EVT RetVT) { argument
1940 } else if (RetVT
[all...]
H A DTargetLowering.cpp124 /// result of type RetVT.
126 TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, argument
158 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
160 bool signExtend = shouldSignExtendTypeInLibCall(RetVT, CallOptions.IsSExt);
396 EVT RetVT = getCmpLibcallReturnType(); local
401 CallOptions.setTypeListBeforeSoften(OpsVT, RetVT, true);
402 auto Call = makeLibCall(DAG, LC1, RetVT, Ops, CallOptions, dl, Chain);
404 NewRHS = DAG.getConstant(0, dl, RetVT);
408 assert(RetVT.isInteger());
409 CCCode = getSetCCInverse(CCCode, RetVT);
[all...]
H A DFastISel.cpp2245 unsigned FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, argument
2247 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
H A DLegalizeVectorTypes.cpp4777 EVT RetVT = WidenEltVT; local
4779 return RetVT;
4801 RetVT = MemVT;
4824 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
4829 return RetVT;
H A DLegalizeIntegerTypes.cpp1954 EVT RetVT = Node->getValueType(0); local
1957 return TLI.makeLibCall(DAG, LC, RetVT, Ops, CallOptions, SDLoc(Node),
2778 EVT RetVT = N->getValueType(0); local
2783 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
H A DSelectionDAGBuilder.cpp6214 EVT RetVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); local
6215 setValue(&I, DAG.getNode(Opcode, sdl, RetVT,
9056 EVT RetVT = OldRetTys[i]; local
9058 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), RetVT);
9059 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), RetVT);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp1130 EVT RetVT = TLI.getValueType(DL, I->getType()); local
1131 if (!VT.isSimple() || !RetVT.isSimple())
1138 if (VT == RetVT) {
1144 Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(),

Completed in 355 milliseconds