| /freebsd-11-stable/sys/mips/idt/ |
| H A D | idtpci.c | 111 #define REG_WRITE(o,v) (REG_READ(o)) = (v) macro
158 REG_WRITE(IDT_PCI_CNTL, IDT_PCI_CNTL_IGM | IDT_PCI_CNTL_EAP |
168 REG_WRITE(IDT_PCI_STATUS, 0);
170 REG_WRITE(IDT_PCI_STATUS_MASK, 0xffffffff);
173 REG_WRITE(IDT_PCI_DAC, 0);
175 REG_WRITE(IDT_PCI_DAS, 0);
176 REG_WRITE(IDT_PCI_DASM, 0x7f);
180 REG_WRITE(IDT_PCI_IIC, 0);
181 REG_WRITE(IDT_PCI_IIM, 0xffffffff);
182 REG_WRITE(IDT_PCI_OI
[all...] |
| /freebsd-11-stable/sys/mips/adm5120/ |
| H A D | if_admsw.c | 222 #define REG_WRITE(o,v) bus_write_4((sc)->mem_res, (o),(v)) macro
280 REG_WRITE(SEND_HBADDR_REG, ADMSW_CDTXHADDR(sc, 0));
281 REG_WRITE(SEND_LBADDR_REG, ADMSW_CDTXLADDR(sc, 0));
282 REG_WRITE(RECV_HBADDR_REG, ADMSW_CDRXHADDR(sc, 0));
283 REG_WRITE(RECV_LBADDR_REG, ADMSW_CDRXLADDR(sc, 0));
297 REG_WRITE(VLAN_G1_REG, i);
299 REG_WRITE(VLAN_G2_REG, i);
308 REG_WRITE(PORT_CONF0_REG,
310 REG_WRITE(CPUP_CONF_REG,
321 REG_WRITE(PHY_CNTL2_RE
[all...] |
| H A D | obio.c | 100 #define REG_WRITE(o,v) (REG_READ(o)) = (v) macro
136 REG_WRITE(ICU_DISABLE_REG, (reg | irqmask));
151 REG_WRITE(ICU_DISABLE_REG, (reg & ~irqmask));
214 REG_WRITE(ICU_ENABLE_REG, ICU_INT_MASK);
372 REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) | irqmask);
374 REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) & ~irqmask);
377 REG_WRITE(ICU_ENABLE_REG, irqmask);
403 REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) & ~irqmask);
405 REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) | irqmask);
410 REG_WRITE(ICU_ENABLE_RE
[all...] |
| /freebsd-11-stable/sys/mips/alchemy/ |
| H A D | obio.c | 100 #define REG_WRITE(o,v) (REG_READ(o)) = (v) macro
215 REG_WRITE(ICU_ENABLE_REG, ICU_INT_MASK);
374 REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) | irqmask);
376 REG_WRITE(ICU_MODE_REG, REG_READ(ICU_MODE_REG) & ~irqmask);
379 REG_WRITE(ICU_ENABLE_REG, irqmask);
402 REG_WRITE(ICU_DISABLE_REG, irqmask);
|
| /freebsd-11-stable/sys/dev/ath/ath_hal/ar5312/ |
| H A D | ar5312reg.h | 31 #define REG_WRITE(_reg,_val) *((volatile uint32_t *)(_reg)) = (_val); macro
|
| /freebsd-11-stable/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_reset.c | 1713 #define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); macro
1717 REG_WRITE(AR_SOC_RST_RESET,
1719 REG_WRITE(AR_SOC_RST_RESET,
1738 #undef REG_WRITE macro
1772 #define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); macro
1817 REG_WRITE(RST_RESET, (REG_READ(RST_RESET) | RTC_RESET));
1819 REG_WRITE(RST_RESET, (REG_READ(RST_RESET) & ~RTC_RESET));
1828 #undef REG_WRITE macro
1953 #define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); macro
1958 REG_WRITE(ATH_GPIO_O
1978 #undef REG_WRITE macro
3083 #define REG_WRITE macro
3100 #undef REG_WRITE macro
5233 #define REG_WRITE macro
5268 #undef REG_WRITE macro
5340 #define REG_WRITE macro
5350 #undef REG_WRITE macro
[all...] |
| H A D | ar9300_attach.c | 774 #define REG_WRITE(_reg, _val) *((volatile u_int32_t *)(_reg)) = (_val); macro
786 #undef REG_WRITE macro
|
| /freebsd-11-stable/sys/arm/broadcom/bcm2835/ |
| H A D | bcm2835_mbox.c | 58 #define REG_WRITE 0x20 /* This is Mailbox 1 address */ macro
222 mbox_write_4(sc, REG_WRITE, MBOX_MSG(chan, data));
|
| /freebsd-11-stable/sys/mips/rt305x/ |
| H A D | obio.c | 95 #define REG_WRITE(o,v) (REG_READ(o)) = (v) macro
|