Searched refs:REGS_SOUTH_TRANSCODER_PORT (Results 1 - 2 of 2) sorted by relevance

/haiku/headers/private/graphics/intel_extreme/
H A Dintel_extreme.h149 #define REGS_SOUTH_TRANSCODER_PORT (5 << REGISTER_BLOCK_SHIFT) macro
976 #define INTEL_TRANSCODER_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT)
977 #define INTEL_TRANSCODER_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT)
978 #define INTEL_TRANSCODER_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT)
979 #define INTEL_TRANSCODER_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT)
980 #define INTEL_TRANSCODER_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT)
981 #define INTEL_TRANSCODER_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT)
982 #define INTEL_TRANSCODER_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT)
983 #define INTEL_TRANSCODER_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT)
984 #define INTEL_TRANSCODER_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT)
[all...]
/haiku/src/add-ons/kernel/drivers/graphics/intel_extreme/
H A Dintel_extreme.cpp682 blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)]
694 blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)]
702 blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)] += VLV_DISPLAY_BASE;
713 TRACE("REGS_SOUTH_TRANSCODER_PORT: 0x%" B_PRIx32 "\n",
714 blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)]);

Completed in 52 milliseconds