/linux-master/arch/hexagon/include/asm/ |
H A D | elf.h | 91 #define CS_COPYREGS(DEST,REGS) \ 93 DEST.cs0 = REGS->cs0;\ 94 DEST.cs1 = REGS->cs1;\ 97 #define CS_COPYREGS(DEST,REGS) 100 #define ELF_CORE_COPY_REGS(DEST, REGS) \ 102 DEST.r0 = REGS->r00; \ 103 DEST.r1 = REGS->r01; \ 104 DEST.r2 = REGS->r02; \ 105 DEST.r3 = REGS->r03; \ 106 DEST.r4 = REGS [all...] |
/linux-master/arch/arm/probes/ |
H A D | decode-arm.c | 156 REGS(0, NOPC, 0, 0, 0)), 163 REGS(0, 0, 0, 0, NOPC)), 167 REGS(0, NOPC, 0, 0, NOPC)), 174 REGS(NOPC, NOPC, 0, 0, NOPC)), 190 REGS(NOPC, NOPC, NOPC, 0, NOPC)), 196 REGS(NOPC, 0, NOPC, 0, NOPC)), 202 REGS(NOPC, NOPC, NOPC, 0, NOPC)), 213 REGS(NOPC, 0, NOPC, 0, NOPC)), 220 REGS(NOPC, NOPC, NOPC, 0, NOPC)), 233 REGS(NOP [all...] |
H A D | decode-thumb.c | 54 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)), 59 REGS(NOSP, 0, 0, 0, NOSPPC)), 79 REGS(NOSPPC, 0, 0, 0, NOSPPC)), 85 REGS(NOPC, 0, 0, 0, NOSPPC)), 90 REGS(0, 0, NOSPPC, 0, NOSPPC)), 105 REGS(SP, 0, SP, 0, NOSPPC)), 114 REGS(SP, 0, NOPC, 0, NOSPPC)), 128 REGS(NOSPPC, 0, NOSPPC, 0, NOSPPC)), 139 REGS(NOSPPC, 0, 0, 0, 0)), 145 REGS(NOP [all...] |
H A D | decode.h | 185 * is specified using the REGS macro, this takes any of the REG_TYPE_* values 189 * REGS(0, ANY, NOPC, 0, ANY) 213 * REGS(ANY, ANY, NOPC, 0, ANY)), 259 /* Alias to allow '0' arg to be used in REGS macro. */ 263 #define REGS(r16, r12, r8, r4, r0) \ macro
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/linux-master/drivers/gpu/drm/amd/display/dmub/src/ |
H A D | dmub_dcn302.c | 36 #define REGS dmub->regs macro
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H A D | dmub_dcn301.c | 36 #define REGS dmub->regs macro
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H A D | dmub_dcn21.c | 36 #define REGS dmub->regs macro
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H A D | dmub_dcn303.c | 37 #define REGS dmub->regs macro
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H A D | dmub_dcn315.c | 42 #define REGS dmub->regs_dcn31 macro
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H A D | dmub_dcn316.c | 42 #define REGS dmub->regs_dcn31 macro
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H A D | dmub_dcn314.c | 42 #define REGS dmub->regs_dcn31 macro
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H A D | dmub_dcn351.c | 13 #define REGS dmub->regs_dcn35 macro
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H A D | dmub_reg.h | 43 #define REG(reg) (REGS)->offset.reg 45 #define FD(reg_field) (REGS)->shift.reg_field, (REGS)->mask.reg_field
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H A D | dmub_dcn30.c | 37 #define REGS dmub->regs macro
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H A D | dmub_dcn20.c | 37 #define REGS dmub->regs macro
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H A D | dmub_dcn31.c | 36 #define REGS dmub->regs_dcn31 macro
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H A D | dmub_dcn32.c | 37 #define REGS dmub->regs_dcn32 macro
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/linux-master/arch/alpha/include/asm/ |
H A D | elf.h | 114 #define ELF_CORE_COPY_REGS(DEST, REGS) \ 115 dump_elf_thread(DEST, REGS, current_thread_info());
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/linux-master/drivers/video/fbdev/nvidia/ |
H A D | nv_setup.c | 295 par->PRAMIN = par->REGS + (0x00710000 / 4); 296 par->PCRTC0 = par->REGS + (0x00600000 / 4); 297 par->PRAMDAC0 = par->REGS + (0x00680000 / 4); 298 par->PFB = par->REGS + (0x00100000 / 4); 299 par->PFIFO = par->REGS + (0x00002000 / 4); 300 par->PGRAPH = par->REGS + (0x00400000 / 4); 301 par->PEXTDEV = par->REGS + (0x00101000 / 4); 302 par->PTIMER = par->REGS + (0x00009000 / 4); 303 par->PMC = par->REGS + (0x00000000 / 4); 304 par->FIFO = par->REGS [all...] |
H A D | nvidia.c | 1205 volatile u32 __iomem *REGS) 1214 id = NV_RD32(REGS, 0x1800); 1284 volatile u32 __iomem *REGS; local 1304 REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); 1305 if (!REGS) { 1310 Chipset = nvidia_get_chipset(pd, REGS); 1349 par->REGS = REGS; 1433 iounmap(REGS); 1451 iounmap(par->REGS); 1204 nvidia_get_chipset(struct pci_dev *pci_dev, volatile u32 __iomem *REGS) argument [all...] |
H A D | nv_type.h | 155 volatile u32 __iomem *REGS; member in struct:nvidia_par
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/linux-master/drivers/media/i2c/ |
H A D | ar0521.c | 672 #define REGS(...) REGS_ENTRY(((const __be16[]){__VA_ARGS__})) macro 678 REGS(be(0x0112), be(0x0808)), /* 8-bit/8-bit mode */ 681 REGS(be(0x301E), be(0x00AA)), 684 REGS(be(0x3042), 688 REGS(be(0x30D2), 694 REGS(be(0x30DA), 700 REGS(be(0x30EE), be(0x1136)), 701 REGS(be(0x30FA), be(0xFD00)), /* GPIO0 = flash, GPIO1 = shutter */ 702 REGS(be(0x3120), be(0x0005)), /* p1 dither enabled for 10bit mode */ 703 REGS(b [all...] |
/linux-master/drivers/gpu/drm/msm/adreno/ |
H A D | a6xx_gpu_state.h | 299 #define REGS(_array, _sel_reg, _sel_val) \ macro 304 REGS(a6xx_registers, 0, 0), 305 REGS(a660_registers, 0, 0), 306 REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0), 307 REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9), 336 REGS(a6xx_ahb_registers, 0, 0); 339 REGS(a6xx_vbif_registers, 0, 0); 342 REGS(a6xx_gbif_registers, 0, 0); 384 REGS(a6xx_gmu_cx_registers, 0, 0), 385 REGS(a6xx_gmu_cx_rscc_register [all...] |
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | uvd_v3_1.c | 211 WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
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H A D | uvd_v4_2.c | 640 WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
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