Searched refs:PWR_BASEADDR_MAC (Results 1 - 8 of 8) sorted by path

/linux-master/drivers/net/wireless/realtek/rtlwifi/
H A Dpwrseqcmd.h19 #define PWR_BASEADDR_MAC 0x00 macro
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Dpwrseq.h46 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1) \
49 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0 \
52 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
55 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0 \
58 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0 \
61 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0) \
64 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0 \
67 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
70 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
75 PWR_BASEADDR_MAC, PWR_CMD_WRIT
[all...]
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dpwrseq.h47 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
50 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
53 PWR_BASEADDR_MAC , PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
56 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
59 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
62 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
65 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(0), 0},
73 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0}, \
76 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
79 PWR_BASEADDR_MAC , PWR_CMD_WRIT
[all...]
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dpwrseq.h46 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\
49 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},\
52 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
55 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
58 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\
61 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
63 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},
71 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
75 PWR_BASEADDR_MAC, PWR_CMD_WRIT
[all...]
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Dpwrseq.h46 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
50 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
54 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS}, \
58 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, \
61 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0}, \
64 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)}, \
67 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
70 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0}, \
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
76 PWR_BASEADDR_MAC, PWR_CMD_WRIT
[all...]
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h26 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
29 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
32 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
35 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
38 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
41 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
45 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
48 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
51 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
54 PWR_BASEADDR_MAC, PWR_CMD_DELA
[all...]
/linux-master/drivers/staging/rtl8723bs/include/
H A DHalPwrSeqCmd.h51 #define PWR_BASEADDR_MAC 0x00 macro
H A Dhal_pwr_seq.h44 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
45 {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
46 {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
47 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital , 1:isolation*/ \
48 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]= 0 and WLSUS_EN 0x04[11]= 0*/ \
49 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* Disable USB suspend */ \
50 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
51 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* Enable USB suspend */ \
52 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]= 1*/ \
53 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRIT
[all...]

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