111814Swpaul/* SPDX-License-Identifier: GPL-2.0 */ 211814Swpaul/* Copyright(c) 2009-2014 Realtek Corporation.*/ 311814Swpaul 411814Swpaul#ifndef __RTL8723BE_PWRSEQ_H__ 511814Swpaul#define __RTL8723BE_PWRSEQ_H__ 611814Swpaul 711814Swpaul#include "../pwrseqcmd.h" 811814Swpaul/** 911814Swpaul * Check document WM-20130425-JackieLau-RTL8723B_Power_Architecture v05.vsd 1011814Swpaul * There are 6 HW Power States: 1111814Swpaul * 0: POFF--Power Off 1211814Swpaul * 1: PDN--Power Down 1311814Swpaul * 2: CARDEMU--Card Emulation 1411814Swpaul * 3: ACT--Active Mode 1511814Swpaul * 4: LPS--Low Power State 1611814Swpaul * 5: SUS--Suspend 1711814Swpaul * 1811814Swpaul * The transision from different states are defined below 1911814Swpaul * TRANS_CARDEMU_TO_ACT 2011814Swpaul * TRANS_ACT_TO_CARDEMU 2111814Swpaul * TRANS_CARDEMU_TO_SUS 2211814Swpaul * TRANS_SUS_TO_CARDEMU 2311814Swpaul * TRANS_CARDEMU_TO_PDN 2411814Swpaul * TRANS_ACT_TO_LPS 2511814Swpaul * TRANS_LPS_TO_ACT 2611814Swpaul * 2711814Swpaul * TRANS_END 2811814Swpaul */ 2911814Swpaul#define RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS 23 3011814Swpaul#define RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS 15 3111814Swpaul#define RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS 15 3211814Swpaul#define RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS 15 3311814Swpaul#define RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS 15 3411814Swpaul#define RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS 15 3511814Swpaul#define RTL8723B_TRANS_ACT_TO_LPS_STEPS 15 3611814Swpaul#define RTL8723B_TRANS_LPS_TO_ACT_STEPS 15 3731404Scharnier#define RTL8723B_TRANS_END_STEPS 1 3831404Scharnier 3950476Speter#define RTL8723B_TRANS_CARDEMU_TO_ACT \ 4031404Scharnier /* format */ \ 4111814Swpaul /* comments here */ \ 4211814Swpaul /* {offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value}, */\ 4311814Swpaul /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ 4411814Swpaul {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 4511814Swpaul PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \ 4611814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 4711814Swpaul /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ 4811814Swpaul {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 4911814Swpaul PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \ 5093590Smike PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ 5111814Swpaul /*Delay 1ms*/ \ 5211814Swpaul {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 5311814Swpaul PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \ 5411814Swpaul PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS}, \ 5511814Swpaul /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ 5611814Swpaul {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 5711814Swpaul PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \ 5811814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, \ 5911814Swpaul /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \ 6011814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 6111814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0}, \ 6211814Swpaul /* Disable USB suspend */ \ 6311814Swpaul {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 6411814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)}, \ 6511814Swpaul /* wait till 0x04[17] = 1 power ready*/ \ 6611814Swpaul {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 6711814Swpaul PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ 6811814Swpaul /* Enable USB suspend */ \ 6911814Swpaul {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 7011814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0}, \ 7111814Swpaul /* release WLON reset 0x04[16]=1*/ \ 7211814Swpaul {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 7311814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 7411814Swpaul /* disable HWPDN 0x04[15]=0*/ \ 7511814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 7611814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \ 7711814Swpaul /* disable WL suspend*/ \ 7811814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 7911814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \ 8011814Swpaul /* polling until return 0*/ \ 8111814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 8211814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 8311814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 8411814Swpaul PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \ 8511814Swpaul /* Enable WL control XTAL setting*/ \ 8611814Swpaul {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 8711814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)}, \ 8890377Simp /*Enable falling edge triggering interrupt*/ \ 8990377Simp {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 9011814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ 9111814Swpaul /*Enable GPIO9 interrupt mode*/ \ 9211814Swpaul {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 9311814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ 9411814Swpaul /*Enable GPIO9 input mode*/ \ 9511814Swpaul {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 9611814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \ 9711814Swpaul /*Enable HSISR GPIO[C:0] interrupt*/ \ 9811814Swpaul {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 9990377Simp PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 10011814Swpaul /*Enable HSISR GPIO9 interrupt*/ \ 10111814Swpaul {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 10211814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ 10311814Swpaul /*For GPIO9 internal pull high setting by test chip*/ \ 10411814Swpaul {0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\ 10511814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)}, \ 10611814Swpaul /*For GPIO9 internal pull high setting*/ \ 10711814Swpaul {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 10811814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)}, 10911814Swpaul 11011814Swpaul#define RTL8723B_TRANS_ACT_TO_CARDEMU \ 11111814Swpaul /* format */ \ 11211814Swpaul /* comments here */ \ 11311814Swpaul /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 11411814Swpaul /*0x1F[7:0] = 0 turn off RF*/ \ 11511814Swpaul {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 11611814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \ 11711814Swpaul /*0x4C[24] = 0x4F[0] = 0, */ \ 11811814Swpaul /*switch DPDT_SEL_P output from register 0x65[2] */ \ 11911814Swpaul {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 12011814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ 12111814Swpaul /*Enable rising edge triggering interrupt*/ \ 12211814Swpaul {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 12311814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \ 12490377Simp /*0x04[9] = 1 turn off MAC by HW state machine*/ \ 12511814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 12611814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ 12711814Swpaul /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ 12811814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 12911814Swpaul PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \ 13011814Swpaul /* Enable BT control XTAL setting*/ \ 13111814Swpaul {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 13211814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0}, \ 13311814Swpaul /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ 13411814Swpaul {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 13511814Swpaul PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ 13611814Swpaul PWR_CMD_WRITE, BIT(5), BIT(5)}, \ 13711814Swpaul /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \ 13811814Swpaul {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 13911814Swpaul PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ 14090377Simp PWR_CMD_WRITE, BIT(0), 0}, 14111814Swpaul 14290377Simp#define RTL8723B_TRANS_CARDEMU_TO_SUS \ 14390377Simp /* format */ \ 14411814Swpaul /* comments here */ \ 14511814Swpaul /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\ 14611814Swpaul /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ 14711814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 14811814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, \ 14911814Swpaul /*0x04[12:11] = 2b'01 enable WL suspend*/ \ 15011814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 15111814Swpaul PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \ 15211814Swpaul PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \ 15311814Swpaul /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ 15411814Swpaul {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 15511814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ 15611814Swpaul /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ 15711814Swpaul {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 15811814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \ 15911814Swpaul /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ 16011814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 16111814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\ 16211814Swpaul /*Set SDIO suspend local register*/ \ 16311814Swpaul {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 16411814Swpaul PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 16511814Swpaul /*wait power state to suspend*/ \ 16611814Swpaul {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 16711814Swpaul PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, 16811814Swpaul 16911814Swpaul#define RTL8723B_TRANS_SUS_TO_CARDEMU \ 17011814Swpaul /* format */ \ 17111814Swpaul /* comments here */ \ 17211814Swpaul /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 17311814Swpaul /*clear suspend enable and power down enable*/ \ 17411814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 17511814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \ 17611814Swpaul /*Set SDIO suspend local register*/ \ 17790377Simp {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 17811814Swpaul PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ 17990377Simp /*wait power state to suspend*/ \ 18090377Simp {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 18111814Swpaul PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ 18290377Simp /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ 18311814Swpaul {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 18411814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ 18511814Swpaul /*0x04[12:11] = 2b'00 disable WL suspend*/ \ 18611814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 18711814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, 18811814Swpaul 18911814Swpaul#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS \ 19011814Swpaul /* format */ \ 19111814Swpaul /* comments here */ \ 19211814Swpaul /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 19311814Swpaul /*0x07=0x20 , SOP option to disable BG/MB*/ \ 19411814Swpaul {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 19511814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \ 19611814Swpaul /*0x04[12:11] = 2b'01 enable WL suspend*/ \ 19711814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 19811814Swpaul PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \ 19911814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \ 20011814Swpaul /*0x04[10] = 1, enable SW LPS*/ \ 20111814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 20211814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, \ 20311814Swpaul /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ 20411814Swpaul {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \ 20511814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, \ 20611814Swpaul /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ 20731404Scharnier {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 20811814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ 20911814Swpaul /*Set SDIO suspend local register*/ \ 21011814Swpaul {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 21111814Swpaul PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \ 21211814Swpaul /*wait power state to suspend*/ \ 21311814Swpaul {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 21411814Swpaul PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, 21511814Swpaul 21611814Swpaul#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU \ 21711814Swpaul /* format */ \ 21811814Swpaul /* comments here */ \ 21911814Swpaul /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 22011814Swpaul /*clear suspend enable and power down enable*/ \ 22111814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 22211814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \ 22311814Swpaul /*Set SDIO suspend local register*/ \ 22411814Swpaul {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 22511814Swpaul PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ 22611814Swpaul /*wait power state to suspend*/ \ 22711814Swpaul {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 22811814Swpaul PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ 22911814Swpaul /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ 23011814Swpaul {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \ 23111814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ 23211814Swpaul /*0x04[12:11] = 2b'00 disable WL suspend*/ \ 23311814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 23411814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \ 23511814Swpaul /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ 23611814Swpaul {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 23711814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ 23811814Swpaul /*PCIe DMA start*/ \ 23911814Swpaul {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 24011814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, 24111814Swpaul 24211814Swpaul#define RTL8723B_TRANS_CARDEMU_TO_PDN \ 24311814Swpaul /* format */ \ 24411814Swpaul /* comments here */ \ 24511814Swpaul /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 24611814Swpaul /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ 24711814Swpaul {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 24811814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \ 24911814Swpaul /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ 25011814Swpaul {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \ 25111814Swpaul PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, \ 25211814Swpaul PWR_CMD_WRITE, 0xFF, 0x20}, \ 25311814Swpaul /* 0x04[16] = 0*/ \ 25411814Swpaul {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 25511814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ 25611814Swpaul /* 0x04[15] = 1*/ \ 25711814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 25811814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, 25911814Swpaul 26011814Swpaul#define RTL8723B_TRANS_PDN_TO_CARDEMU \ 26131404Scharnier /* format */ \ 26211814Swpaul /* comments here */ \ 26311814Swpaul /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 26411814Swpaul /* 0x04[15] = 0*/ \ 26511814Swpaul {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 26611814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, 26711814Swpaul 26811814Swpaul#define RTL8723B_TRANS_ACT_TO_LPS \ 26911814Swpaul /* format */ \ 27011814Swpaul /* comments here */ \ 27111814Swpaul /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 27211814Swpaul /*PCIe DMA stop*/ \ 27311814Swpaul {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 27411814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \ 27511814Swpaul /*Tx Pause*/ \ 27611814Swpaul {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 27711814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \ 27811814Swpaul /*Should be zero if no packet is transmitting*/ \ 27911814Swpaul {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 28011814Swpaul PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ 28111814Swpaul /*Should be zero if no packet is transmitting*/ \ 28211814Swpaul {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 28311814Swpaul PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ 28411814Swpaul /*Should be zero if no packet is transmitting*/ \ 28511814Swpaul {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 28611814Swpaul PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ 28790377Simp /*Should be zero if no packet is transmitting*/ \ 28811814Swpaul {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 28990377Simp PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \ 29090377Simp /*CCK and OFDM are disabled,and clock are gated*/ \ 29111814Swpaul {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 29211814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ 29311814Swpaul /*Delay 1us*/ \ 29420387Swpaul {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 29511814Swpaul PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \ 29611814Swpaul /*Whole BB is reset*/ \ 29711814Swpaul {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 29811814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \ 29911814Swpaul /*Reset MAC TRX*/ \ 30011814Swpaul {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 30111814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03}, \ 30211814Swpaul /*check if removed later*/ \ 30311814Swpaul {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 30411814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \ 30511814Swpaul /*When driver enter Sus/ Disable, enable LOP for BT*/ \ 30611814Swpaul {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 30711814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, \ 30811814Swpaul /*Respond TxOK to scheduler*/ \ 30911814Swpaul {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 31011814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, 31111814Swpaul 31211814Swpaul#define RTL8723B_TRANS_LPS_TO_ACT \ 31311814Swpaul /* format */ \ 31411814Swpaul /* comments here */ \ 31511814Swpaul /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 31611814Swpaul /*SDIO RPWM*/ \ 31711814Swpaul {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 31811814Swpaul PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, \ 31911814Swpaul /*USB RPWM*/ \ 32011814Swpaul {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \ 32111814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \ 32211814Swpaul /*PCIe RPWM*/ \ 32311814Swpaul {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 32411814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \ 32511814Swpaul /*Delay*/ \ 32611814Swpaul {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 32711814Swpaul PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \ 32811814Swpaul /*. 0x08[4] = 0 switch TSF to 40M*/ \ 32911814Swpaul {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 33011814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ 33111814Swpaul /*Polling 0x109[7]=0 TSF in 40M*/ \ 33211814Swpaul {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 33311814Swpaul PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \ 33411814Swpaul /*. 0x29[7:6] = 2b'00 enable BB clock*/ \ 33511814Swpaul {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 33611814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \ 33711814Swpaul /*. 0x101[1] = 1*/ \ 33811814Swpaul {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 33911814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \ 34011814Swpaul /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \ 34111814Swpaul {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 34211814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \ 34311814Swpaul /*. 0x02[1:0] = 2b'11 enable BB macro*/ \ 34411814Swpaul {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 34511814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \ 34611814Swpaul /*. 0x522 = 0*/ \ 34711814Swpaul {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 34811814Swpaul PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, 34911814Swpaul 35011814Swpaul#define RTL8723B_TRANS_END \ 35111814Swpaul /* format */ \ 35211814Swpaul /* comments here */ \ 35311814Swpaul /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 35411814Swpaul {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, \ 35511814Swpaul PWR_CMD_END, 0, 0}, 35611814Swpaul 35711814Swpaulextern struct wlan_pwr_cfg rtl8723B_power_on_flow 35811814Swpaul [RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS + 35911814Swpaul RTL8723B_TRANS_END_STEPS]; 36011814Swpaulextern struct wlan_pwr_cfg rtl8723B_radio_off_flow 36111814Swpaul [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + 36211814Swpaul RTL8723B_TRANS_END_STEPS]; 36311814Swpaulextern struct wlan_pwr_cfg rtl8723B_card_disable_flow 36411814Swpaul [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + 365 RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + 366 RTL8723B_TRANS_END_STEPS]; 367extern struct wlan_pwr_cfg rtl8723B_card_enable_flow 368 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + 369 RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + 370 RTL8723B_TRANS_END_STEPS]; 371extern struct wlan_pwr_cfg rtl8723B_suspend_flow 372 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + 373 RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS + 374 RTL8723B_TRANS_END_STEPS]; 375extern struct wlan_pwr_cfg rtl8723B_resume_flow 376 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + 377 RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS + 378 RTL8723B_TRANS_END_STEPS]; 379extern struct wlan_pwr_cfg rtl8723B_hwpdn_flow 380 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + 381 RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + 382 RTL8723B_TRANS_END_STEPS]; 383extern struct wlan_pwr_cfg rtl8723B_enter_lps_flow 384 [RTL8723B_TRANS_ACT_TO_LPS_STEPS + 385 RTL8723B_TRANS_END_STEPS]; 386extern struct wlan_pwr_cfg rtl8723B_leave_lps_flow 387 [RTL8723B_TRANS_LPS_TO_ACT_STEPS + 388 RTL8723B_TRANS_END_STEPS]; 389 390/* RTL8723 Power Configuration CMDs for PCIe interface */ 391#define RTL8723_NIC_PWR_ON_FLOW rtl8723B_power_on_flow 392#define RTL8723_NIC_RF_OFF_FLOW rtl8723B_radio_off_flow 393#define RTL8723_NIC_DISABLE_FLOW rtl8723B_card_disable_flow 394#define RTL8723_NIC_ENABLE_FLOW rtl8723B_card_enable_flow 395#define RTL8723_NIC_SUSPEND_FLOW rtl8723B_suspend_flow 396#define RTL8723_NIC_RESUME_FLOW rtl8723B_resume_flow 397#define RTL8723_NIC_PDN_FLOW rtl8723B_hwpdn_flow 398#define RTL8723_NIC_LPS_ENTER_FLOW rtl8723B_enter_lps_flow 399#define RTL8723_NIC_LPS_LEAVE_FLOW rtl8723B_leave_lps_flow 400 401#endif 402