1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2009-2014  Realtek Corporation.*/
3
4#ifndef __RTL8723BE_PWRSEQ_H__
5#define __RTL8723BE_PWRSEQ_H__
6
7#include "../pwrseqcmd.h"
8/**
9 *	Check document WM-20130425-JackieLau-RTL8723B_Power_Architecture v05.vsd
10 *	There are 6 HW Power States:
11 *	0: POFF--Power Off
12 *	1: PDN--Power Down
13 *	2: CARDEMU--Card Emulation
14 *	3: ACT--Active Mode
15 *	4: LPS--Low Power State
16 *	5: SUS--Suspend
17 *
18 *	The transision from different states are defined below
19 *	TRANS_CARDEMU_TO_ACT
20 *	TRANS_ACT_TO_CARDEMU
21 *	TRANS_CARDEMU_TO_SUS
22 *	TRANS_SUS_TO_CARDEMU
23 *	TRANS_CARDEMU_TO_PDN
24 *	TRANS_ACT_TO_LPS
25 *	TRANS_LPS_TO_ACT
26 *
27 *	TRANS_END
28 */
29#define	RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS	23
30#define	RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS	15
31#define	RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS	15
32#define	RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS	15
33#define	RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS	15
34#define	RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS	15
35#define	RTL8723B_TRANS_ACT_TO_LPS_STEPS		15
36#define	RTL8723B_TRANS_LPS_TO_ACT_STEPS		15
37#define	RTL8723B_TRANS_END_STEPS		1
38
39#define RTL8723B_TRANS_CARDEMU_TO_ACT					\
40	/* format */							\
41	/* comments here */						\
42	/* {offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value}, */\
43	/*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/  \
44	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
45	 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK,				\
46	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},		\
47	/*0x67[0] = 0 to disable BT_GPS_SEL pins*/			\
48	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
49	 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK,				\
50	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},			\
51	/*Delay 1ms*/							\
52	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
53	 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK,				\
54	 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},		\
55	/*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/   \
56	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
57	 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK,				\
58	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0},			\
59	/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/		\
60	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
61	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0},	\
62	/* Disable USB suspend */					\
63	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
64	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)},		\
65	/* wait till 0x04[17] = 1    power ready*/			\
66	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
67	 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},		\
68	/* Enable USB suspend */					\
69	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
70	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0},			\
71	/* release WLON reset  0x04[16]=1*/				\
72	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
73	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},		\
74	/* disable HWPDN 0x04[15]=0*/					\
75	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
76	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},			\
77	/* disable WL suspend*/						\
78	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
79	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},		\
80	/* polling until return 0*/					\
81	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
82	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},		\
83	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
84	 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},			\
85	/* Enable WL control XTAL setting*/				\
86	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
87	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},		\
88	/*Enable falling edge triggering interrupt*/			\
89	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
90	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},		\
91	/*Enable GPIO9 interrupt mode*/					\
92	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
93	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},		\
94	/*Enable GPIO9 input mode*/					\
95	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
96	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},			\
97	/*Enable HSISR GPIO[C:0] interrupt*/				\
98	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
99	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},		\
100	/*Enable HSISR GPIO9 interrupt*/				\
101	{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
102	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},		\
103	/*For GPIO9 internal pull high setting by test chip*/		\
104	{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
105	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)},		\
106	/*For GPIO9 internal pull high setting*/			\
107	{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
108	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},
109
110#define RTL8723B_TRANS_ACT_TO_CARDEMU					\
111	/* format */							\
112	/* comments here */						\
113	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
114	/*0x1F[7:0] = 0 turn off RF*/					\
115	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
116	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},			\
117	/*0x4C[24] = 0x4F[0] = 0, */					\
118	/*switch DPDT_SEL_P output from register 0x65[2] */		\
119	{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
120	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},			\
121	/*Enable rising edge triggering interrupt*/			\
122	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
123	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},			\
124	 /*0x04[9] = 1 turn off MAC by HW state machine*/		\
125	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
126	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},		\
127	 /*wait till 0x04[9] = 0 polling until return 0 to disable*/	\
128	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
129	 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},			\
130	/* Enable BT control XTAL setting*/				\
131	{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
132	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0},			\
133	/*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/		\
134	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
135	 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,	\
136	 PWR_CMD_WRITE, BIT(5), BIT(5)},				\
137	/*0x20[0] = 1b'0 disable LDOA12 MACRO block*/			\
138	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
139	 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,	\
140	 PWR_CMD_WRITE, BIT(0), 0},
141
142#define RTL8723B_TRANS_CARDEMU_TO_SUS					\
143	/* format */							\
144	/* comments here */						\
145	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
146	/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/		\
147	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
148	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, \
149	/*0x04[12:11] = 2b'01 enable WL suspend*/			\
150	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
151	 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC,	\
152	 PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},			\
153	/*0x23[4] = 1b'1 12H LDO enter sleep mode*/			\
154	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
155	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},		\
156	/*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/   \
157	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
158	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20},			\
159	/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/		\
160	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
161	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
162	/*Set SDIO suspend local register*/				\
163	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
164	 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)},		\
165	/*wait power state to suspend*/					\
166	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
167	 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
168
169#define RTL8723B_TRANS_SUS_TO_CARDEMU					\
170	/* format */							\
171	/* comments here */						\
172	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
173	/*clear suspend enable and power down enable*/			\
174	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
175	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0},		\
176	/*Set SDIO suspend local register*/				\
177	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
178	 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},			\
179	/*wait power state to suspend*/					\
180	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
181	 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},		\
182	/*0x23[4] = 1b'0 12H LDO enter normal mode*/			\
183	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
184	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},			\
185	/*0x04[12:11] = 2b'00 disable WL suspend*/			\
186	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
187	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
188
189#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS				\
190	/* format */							\
191	/* comments here */						\
192	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
193	/*0x07=0x20 , SOP option to disable BG/MB*/			\
194	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
195	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20},			\
196	/*0x04[12:11] = 2b'01 enable WL suspend*/			\
197	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
198	 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK,				\
199	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},	\
200	/*0x04[10] = 1, enable SW LPS*/					\
201	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
202	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)},		\
203	/*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/			\
204	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,	\
205	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1},			\
206	/*0x23[4] = 1b'1 12H LDO enter sleep mode*/			\
207	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
208	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},		\
209	/*Set SDIO suspend local register*/				\
210	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
211	 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)},		\
212	/*wait power state to suspend*/					\
213	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
214	 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
215
216#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU				\
217	/* format */							\
218	/* comments here */						\
219	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
220	/*clear suspend enable and power down enable*/			\
221	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
222	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0},		\
223	/*Set SDIO suspend local register*/				\
224	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
225	 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},			\
226	/*wait power state to suspend*/					\
227	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
228	 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},		\
229	/*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/			\
230	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,	\
231	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},			\
232	/*0x04[12:11] = 2b'00 disable WL suspend*/			\
233	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
234	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},		\
235	/*0x23[4] = 1b'0 12H LDO enter normal mode*/			\
236	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
237	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},			\
238	/*PCIe DMA start*/						\
239	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
240	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
241
242#define RTL8723B_TRANS_CARDEMU_TO_PDN					\
243	/* format */							\
244	/* comments here */						\
245	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
246	/*0x23[4] = 1b'1 12H LDO enter sleep mode*/			\
247	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
248	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)},		\
249	/*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/	\
250	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
251	 PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC,	\
252	 PWR_CMD_WRITE, 0xFF, 0x20},					\
253	/* 0x04[16] = 0*/						\
254	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
255	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},			\
256	/* 0x04[15] = 1*/						\
257	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
258	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},
259
260#define RTL8723B_TRANS_PDN_TO_CARDEMU					\
261	/* format */							\
262	/* comments here */						\
263	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
264	/* 0x04[15] = 0*/						\
265	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
266	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},
267
268#define RTL8723B_TRANS_ACT_TO_LPS					\
269	/* format */							\
270	/* comments here */						\
271	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
272	/*PCIe DMA stop*/						\
273	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
274	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},			\
275	/*Tx Pause*/							\
276	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
277	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},			\
278	/*Should be zero if no packet is transmitting*/			\
279	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
280	 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},			\
281	/*Should be zero if no packet is transmitting*/			\
282	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
283	 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},			\
284	/*Should be zero if no packet is transmitting*/			\
285	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
286	 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},			\
287	/*Should be zero if no packet is transmitting*/			\
288	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
289	 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},			\
290	/*CCK and OFDM are disabled,and clock are gated*/		\
291	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
292	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},			\
293	/*Delay 1us*/							\
294	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
295	 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},		\
296	/*Whole BB is reset*/						\
297	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
298	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},			\
299	/*Reset MAC TRX*/						\
300	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
301	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},			\
302	/*check if removed later*/					\
303	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
304	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},			\
305	/*When driver enter Sus/ Disable, enable LOP for BT*/		\
306	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
307	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},			\
308	/*Respond TxOK to scheduler*/					\
309	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
310	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},
311
312#define RTL8723B_TRANS_LPS_TO_ACT					\
313	/* format */							\
314	/* comments here */						\
315	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
316	/*SDIO RPWM*/							\
317	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
318	 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84},			\
319	/*USB RPWM*/							\
320	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,	\
321	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84},			\
322	/*PCIe RPWM*/							\
323	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
324	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84},			\
325	/*Delay*/							\
326	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
327	 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS},		\
328	/*.	0x08[4] = 0		 switch TSF to 40M*/		\
329	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
330	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},			\
331	/*Polling 0x109[7]=0  TSF in 40M*/				\
332	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
333	 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0},			\
334	/*.	0x29[7:6] = 2b'00	 enable BB clock*/		\
335	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
336	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0},		\
337	/*.	0x101[1] = 1*/						\
338	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
339	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},		\
340	/*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/		\
341	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
342	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},			\
343	/*.	0x02[1:0] = 2b'11	 enable BB macro*/		\
344	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
345	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
346	/*.	0x522 = 0*/						\
347	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
348	 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
349
350#define RTL8723B_TRANS_END						\
351	/* format */							\
352	/* comments here */						\
353	/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
354	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0,	\
355	 PWR_CMD_END, 0, 0},
356
357extern struct wlan_pwr_cfg rtl8723B_power_on_flow
358				[RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS +
359				 RTL8723B_TRANS_END_STEPS];
360extern struct wlan_pwr_cfg rtl8723B_radio_off_flow
361				[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
362				 RTL8723B_TRANS_END_STEPS];
363extern struct wlan_pwr_cfg rtl8723B_card_disable_flow
364				[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
365				 RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS +
366				 RTL8723B_TRANS_END_STEPS];
367extern struct wlan_pwr_cfg rtl8723B_card_enable_flow
368				[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
369				 RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS +
370				 RTL8723B_TRANS_END_STEPS];
371extern struct wlan_pwr_cfg rtl8723B_suspend_flow
372				[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
373				 RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS +
374				 RTL8723B_TRANS_END_STEPS];
375extern struct wlan_pwr_cfg rtl8723B_resume_flow
376				[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
377				 RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS +
378				 RTL8723B_TRANS_END_STEPS];
379extern struct wlan_pwr_cfg rtl8723B_hwpdn_flow
380				[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
381				 RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS +
382				 RTL8723B_TRANS_END_STEPS];
383extern struct wlan_pwr_cfg rtl8723B_enter_lps_flow
384				[RTL8723B_TRANS_ACT_TO_LPS_STEPS +
385				 RTL8723B_TRANS_END_STEPS];
386extern struct wlan_pwr_cfg rtl8723B_leave_lps_flow
387				[RTL8723B_TRANS_LPS_TO_ACT_STEPS +
388				 RTL8723B_TRANS_END_STEPS];
389
390/* RTL8723 Power Configuration CMDs for PCIe interface */
391#define RTL8723_NIC_PWR_ON_FLOW		rtl8723B_power_on_flow
392#define RTL8723_NIC_RF_OFF_FLOW		rtl8723B_radio_off_flow
393#define RTL8723_NIC_DISABLE_FLOW	rtl8723B_card_disable_flow
394#define RTL8723_NIC_ENABLE_FLOW		rtl8723B_card_enable_flow
395#define RTL8723_NIC_SUSPEND_FLOW	rtl8723B_suspend_flow
396#define RTL8723_NIC_RESUME_FLOW		rtl8723B_resume_flow
397#define RTL8723_NIC_PDN_FLOW		rtl8723B_hwpdn_flow
398#define RTL8723_NIC_LPS_ENTER_FLOW	rtl8723B_enter_lps_flow
399#define RTL8723_NIC_LPS_LEAVE_FLOW	rtl8723B_leave_lps_flow
400
401#endif
402