/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ExpandImm.h | 25 uint64_t Op2; member in struct:llvm::AArch64_IMM::ImmInsnModel
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H A D | AArch64SelectionDAGInfo.h | 27 SDValue Chain, SDValue Op1, SDValue Op2,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
H A D | LanaiMCCodeEmitter.cpp | 142 const MCOperand Op2 = Inst.getOperand(2); local 145 ((Op2.isImm() && Op2.getImm() != 0) || 146 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) 153 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || 154 (Op2.isReg() && Op2 190 const MCOperand Op2 = Inst.getOperand(OpNo + 1); local 222 const MCOperand Op2 = Inst.getOperand(OpNo + 1); local 261 const MCOperand Op2 = Inst.getOperand(OpNo + 1); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblySelectionDAGInfo.h | 26 SDValue Chain, SDValue Op1, SDValue Op2, 32 SDValue Chain, SDValue Op1, SDValue Op2, 37 SDValue Chain, SDValue Op1, SDValue Op2,
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H A D | WebAssemblySelectionDAGInfo.cpp | 37 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2, 40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, Align, 36 EmitTargetCodeForMemmove( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool IsVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
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H A D | WebAssemblyPeephole.cpp | 162 const auto &Op2 = MI.getOperand(2); local 163 if (!Op2.isReg()) 168 Register NewReg = Op2.getReg();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 240 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { argument 253 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); 258 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, argument 268 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); 346 unsigned Op1, Op2; local 347 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 352 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 359 unsigned Op1, Op2; local 360 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 365 DecodeGRRegsRegisterClass(Inst, Op2, Addres 372 unsigned Op1, Op2; local 385 unsigned Op1, Op2; local 399 unsigned Op1, Op2; local 412 unsigned Op1, Op2; local 425 unsigned Op1, Op2; local 510 unsigned Op1, Op2; local 524 unsigned Op1, Op2; local 538 unsigned Op1, Op2, Op3; local 551 unsigned Op1, Op2, Op3; local 564 unsigned Op1, Op2, Op3; local 577 unsigned Op1, Op2, Op3; local 590 unsigned Op1, Op2, Op3; local 604 unsigned Op1, Op2, Op3; local 619 unsigned Op1, Op2, Op3; local 633 unsigned Op1, Op2, Op3; local 647 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local 681 unsigned Op1, Op2, Op3, Op4, Op5; local 701 unsigned Op1, Op2, Op3; local 720 unsigned Op1, Op2, Op3; local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.cpp | 135 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; 141 Ops[5].getAsInteger(10, Op2); 142 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 153 uint32_t Op2 = Bits & 0x7; local 156 utostr(CRm) + "_" + utostr(Op2);
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/freebsd-11-stable/sys/contrib/dev/acpica/compiler/ |
H A D | asltree.c | 608 * Op2 - Second peer 619 ACPI_PARSE_OBJECT *Op2) 627 Op2, Op2 ? UtGetOpName(Op2->Asl.ParseOpcode) : NULL); 630 if ((!Op1) && (!Op2)) 638 if (!Op2) 645 return (Op2); 648 if (Op1 == Op2) 658 Op1->Asl.Parent = Op2 617 TrLinkPeerOp( ACPI_PARSE_OBJECT *Op1, ACPI_PARSE_OBJECT *Op2) argument 754 TrLinkChildOp( ACPI_PARSE_OBJECT *Op1, ACPI_PARSE_OBJECT *Op2) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreSelectionDAGInfo.h | 25 SDValue Chain, SDValue Op1, SDValue Op2,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | DFAPacketizer.cpp | 283 const MachineMemOperand &Op2, 285 if (!Op1.getValue() || !Op2.getValue()) 288 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); 290 int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset; 295 MemoryLocation(Op2.getValue(), Overlapb, 296 UseTBAA ? Op2.getAAInfo() : AAMDNodes())); 308 for (const MachineMemOperand *Op2 : MI2.memoperands()) 309 if (alias(*Op1, *Op2, UseTBAA)) 282 alias(const MachineMemOperand &Op1, const MachineMemOperand &Op2, bool UseTBAA) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiMemAluCombiner.cpp | 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { argument 171 if (Op1.getType() != Op2.getType()) 176 return Op1.getReg() == Op2.getReg(); 178 return Op1.getImm() == Op2.getImm(); 294 MachineOperand &Op2 = AluIter->getOperand(2); local 301 if (Op2.isImm()) { 312 // Check that the Op2 would fit in the immediate field of the 314 ((IsSpls && isInt<10>(Op2.getImm())) || 315 (!IsSpls && isInt<16>(Op2.getImm())))) || 316 Offset.getImm() == Op2 [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGTargetInfo.h | 53 SDValue Op2, SDValue Op3, 69 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, 82 SDValue Op2, SDValue Op3, 94 SDValue Op1, SDValue Op2, SDValue Op3, 131 SDValue Op1, SDValue Op2, 51 EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 67 EmitTargetCodeForMemmove( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 80 EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument 93 EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument 130 EmitTargetCodeForStrcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/ |
H A D | BPFAsmParser.cpp | 268 BPFOperand &Op2 = (BPFOperand &)*Operands[2]; local 270 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() 272 && (Op2.getToken() == "-" || Op2.getToken() == "be16" 273 || Op2.getToken() == "be32" || Op2.getToken() == "be64" 274 || Op2.getToken() == "le16" || Op2.getToken() == "le32" 275 || Op2.getToken() == "le64")
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/ |
H A D | BPFMCCodeEmitter.cpp | 166 MCOperand Op2 = MI.getOperand(2); local 167 assert(Op2.isImm() && "Second operand is not immediate."); 168 Encoding |= Op2.getImm() & 0xffff;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIOptimizeExecMaskingPreRA.cpp | 232 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1); local 233 if (Op1->isImm() && Op2->isReg()) 234 std::swap(Op1, Op2); 235 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1) 248 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1); 250 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() || 251 Op1->getImm() != 0 || Op2->getImm() != 1)
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H A D | SIInsertSkips.cpp | 372 MachineOperand &Op2 = A->getOperand(2); local 373 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) { 379 if (Op2.isImm() && Op2.getImm() != -1) 383 if (Op2.isReg()) { 384 SReg = Op2.getReg(); 401 if (!ReadsSreg && Op2.isKill()) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 56 SDValue Chain, SDValue Op1, SDValue Op2,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCBranchCoalescing.cpp | 337 const MachineOperand &Op2 = OpList2[i]; local 340 << "Op2: " << Op2 << "\n"); local 342 if (Op1.isIdenticalTo(Op2)) { 352 LLVM_DEBUG(dbgs() << "Op1 and Op2 are identical!\n"); 359 if (Op1.isReg() && Op2.isReg() && 361 Register::isVirtualRegister(Op2.getReg())) { 363 MachineInstr *Op2Def = MRI->getVRegDef(Op2.getReg());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
H A D | BypassSlowDivision.cpp | 89 Value *insertOperandRuntimeCheck(Value *Op1, Value *Op2); 328 Value *FastDivInsertionTask::insertOperandRuntimeCheck(Value *Op1, Value *Op2) { 329 assert((Op1 || Op2) && "Nothing to check"); 333 if (Op1 && Op2) 334 OrV = Builder.CreateOr(Op1, Op2); 336 OrV = Op1 ? Op1 : Op2;
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/DebugInfo/DWARF/ |
H A D | DWARFExpression.h | 68 Encoding Op2 = SizeNA) 71 Op[1] = Op2;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonSplitDouble.cpp | 346 const MachineOperand &Op2 = MI->getOperand(2); local 348 int32_t Prof2 = Op2.isImm() ? profitImm(Op2.getImm()) : 0; 731 MachineOperand &Op2 = MI->getOperand(2); local 748 if (!Op2.isReg()) { 750 .add(Op2); 753 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); 783 MachineOperand &Op2 local 907 MachineOperand &Op2 = MI->getOperand(2); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Transforms/Scalar/ |
H A D | NaryReassociate.h | 149 // Tries to match Op1 and Op2 by using V. 150 bool matchTernaryOp(BinaryOperator *I, Value *V, Value *&Op1, Value *&Op2);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/ |
H A D | ProfileSummary.cpp | 130 ConstantAsMetadata *Op2 = local 133 if (!Op0 || !Op1 || !Op2) 137 cast<ConstantInt>(Op2->getValue())->getZExtValue());
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/MCParser/ |
H A D | MCTargetAsmParser.h | 454 const MCParsedAsmOperand &Op2) const { 455 assert(Op1.isReg() && Op2.isReg() && "Operands not all regs"); 456 return Op1.getReg() == Op2.getReg();
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