1//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides basic encoding and assembly information for AArch64.
10//
11//===----------------------------------------------------------------------===//
12#include "AArch64BaseInfo.h"
13#include "llvm/ADT/ArrayRef.h"
14#include "llvm/ADT/SmallVector.h"
15#include "llvm/ADT/StringExtras.h"
16#include "llvm/Support/Regex.h"
17
18using namespace llvm;
19
20namespace llvm {
21  namespace AArch64AT {
22#define GET_AT_IMPL
23#include "AArch64GenSystemOperands.inc"
24  }
25}
26
27
28namespace llvm {
29  namespace AArch64DB {
30#define GET_DB_IMPL
31#include "AArch64GenSystemOperands.inc"
32  }
33}
34
35namespace llvm {
36  namespace AArch64DC {
37#define GET_DC_IMPL
38#include "AArch64GenSystemOperands.inc"
39  }
40}
41
42namespace llvm {
43  namespace AArch64IC {
44#define GET_IC_IMPL
45#include "AArch64GenSystemOperands.inc"
46  }
47}
48
49namespace llvm {
50  namespace AArch64ISB {
51#define GET_ISB_IMPL
52#include "AArch64GenSystemOperands.inc"
53  }
54}
55
56namespace llvm {
57  namespace AArch64TSB {
58#define GET_TSB_IMPL
59#include "AArch64GenSystemOperands.inc"
60  }
61}
62
63namespace llvm {
64  namespace AArch64PRCTX {
65#define GET_PRCTX_IMPL
66#include "AArch64GenSystemOperands.inc"
67  }
68}
69
70namespace llvm {
71  namespace AArch64PRFM {
72#define GET_PRFM_IMPL
73#include "AArch64GenSystemOperands.inc"
74  }
75}
76
77namespace llvm {
78  namespace AArch64SVEPRFM {
79#define GET_SVEPRFM_IMPL
80#include "AArch64GenSystemOperands.inc"
81  }
82}
83
84namespace llvm {
85  namespace AArch64SVEPredPattern {
86#define GET_SVEPREDPAT_IMPL
87#include "AArch64GenSystemOperands.inc"
88  }
89}
90
91namespace llvm {
92  namespace AArch64ExactFPImm {
93#define GET_EXACTFPIMM_IMPL
94#include "AArch64GenSystemOperands.inc"
95  }
96}
97
98namespace llvm {
99  namespace AArch64PState {
100#define GET_PSTATE_IMPL
101#include "AArch64GenSystemOperands.inc"
102  }
103}
104
105namespace llvm {
106  namespace AArch64PSBHint {
107#define GET_PSB_IMPL
108#include "AArch64GenSystemOperands.inc"
109  }
110}
111
112namespace llvm {
113  namespace AArch64BTIHint {
114#define GET_BTI_IMPL
115#include "AArch64GenSystemOperands.inc"
116  }
117}
118
119namespace llvm {
120  namespace AArch64SysReg {
121#define GET_SYSREG_IMPL
122#include "AArch64GenSystemOperands.inc"
123  }
124}
125
126uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) {
127  // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
128  static const Regex GenericRegPattern("^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$");
129
130  std::string UpperName = Name.upper();
131  SmallVector<StringRef, 5> Ops;
132  if (!GenericRegPattern.match(UpperName, &Ops))
133    return -1;
134
135  uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
136  uint32_t Bits;
137  Ops[1].getAsInteger(10, Op0);
138  Ops[2].getAsInteger(10, Op1);
139  Ops[3].getAsInteger(10, CRn);
140  Ops[4].getAsInteger(10, CRm);
141  Ops[5].getAsInteger(10, Op2);
142  Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
143
144  return Bits;
145}
146
147std::string AArch64SysReg::genericRegisterString(uint32_t Bits) {
148  assert(Bits < 0x10000);
149  uint32_t Op0 = (Bits >> 14) & 0x3;
150  uint32_t Op1 = (Bits >> 11) & 0x7;
151  uint32_t CRn = (Bits >> 7) & 0xf;
152  uint32_t CRm = (Bits >> 3) & 0xf;
153  uint32_t Op2 = Bits & 0x7;
154
155  return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
156         utostr(CRm) + "_" + utostr(Op2);
157}
158
159namespace llvm {
160  namespace AArch64TLBI {
161#define GET_TLBI_IMPL
162#include "AArch64GenSystemOperands.inc"
163  }
164}
165