Target/Hexagon/HexagonSplitDouble.cpp

346       const MachineOperand &Op2 = MI->getOperand(2);
348       int32_t Prof2 = Op2.isImm() ? profitImm(Op2.getImm()) : 0;
731   MachineOperand &Op2 = MI->getOperand(2);
748   if (!Op2.isReg()) {
750       .add(Op2);
753       .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
783   MachineOperand &Op2 = MI->getOperand(2);
784   assert(Op0.isReg() && Op1.isReg() && Op2.isImm());
785   int64_t Sh64 = Op2.getImm();
907   MachineOperand &Op2 = MI->getOperand(2);
909   assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());
923   unsigned RS2 = getRegState(Op2);
929   // Op0 = S2_asl_i_p_or Op1, Op2, Op3
930   // means:  Op0 = or (Op1, asl(Op2, Op3))
947       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);
950       .addReg(Op2.getReg(), RS2, HiSR);
954       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
958       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
967       .addReg(Op2.getReg(), RS2, HiSR)
978       .addReg(Op2.getReg(), RS2, LoSR);
989       .addReg(Op2.getReg(), RS2, LoSR)