Searched refs:MP1_BASE__INST0_SEG4 (Results 1 - 16 of 16) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.c42 #define MP1_BASE__INST0_SEG4 0x00E40000 macro
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_smu.c42 #define MP1_BASE__INST0_SEG4 0x00E40000 macro
/linux-master/drivers/gpu/drm/amd/include/
H A Dcyan_skillfish_ip_offset.h463 #define MP1_BASE__INST0_SEG4 0 macro
H A Dnavi10_ip_offset.h523 #define MP1_BASE__INST0_SEG4 0 macro
H A Dvega20_ip_offset.h548 #define MP1_BASE__INST0_SEG4 0 macro
H A Dyellow_carp_offset.h879 #define MP1_BASE__INST0_SEG4 0x00E40000 macro
H A Drenoir_ip_offset.h951 #define MP1_BASE__INST0_SEG4 0x00F00000 macro
H A Dvega10_ip_offset.h367 #define MP1_BASE__INST0_SEG4 0 macro
H A Dsienna_cichlid_ip_offset.h708 #define MP1_BASE__INST0_SEG4 0x0243FC00 macro
H A Dbeige_goby_ip_offset.h835 #define MP1_BASE__INST0_SEG4 0x0243FC00 macro
H A Dnavi12_ip_offset.h701 #define MP1_BASE__INST0_SEG4 0x02400400 macro
H A Dnavi14_ip_offset.h701 #define MP1_BASE__INST0_SEG4 0x0243FC00 macro
H A Ddimgrey_cavefish_ip_offset.h708 #define MP1_BASE__INST0_SEG4 0x02400400 macro
H A Daldebaran_ip_offset.h1007 #define MP1_BASE__INST0_SEG4 0x0243FC00 macro
H A Dvangogh_ip_offset.h958 #define MP1_BASE__INST0_SEG4 0x00E40000 macro
H A Darct_ip_offset.h696 #define MP1_BASE__INST0_SEG4 0x00EC0000 macro

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