Searched refs:MP1_BASE__INST0_SEG1 (Results 1 - 16 of 16) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.c39 #define MP1_BASE__INST0_SEG1 0x0243FC00 macro
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_smu.c39 #define MP1_BASE__INST0_SEG1 0x0243FC00 macro
/linux-master/drivers/gpu/drm/amd/include/
H A Dcyan_skillfish_ip_offset.h460 #define MP1_BASE__INST0_SEG1 0 macro
H A Dnavi10_ip_offset.h520 #define MP1_BASE__INST0_SEG1 0 macro
H A Dvega20_ip_offset.h545 #define MP1_BASE__INST0_SEG1 0 macro
H A Dyellow_carp_offset.h876 #define MP1_BASE__INST0_SEG1 0x0243FC00 macro
H A Drenoir_ip_offset.h948 #define MP1_BASE__INST0_SEG1 0x02400400 macro
H A Dvega10_ip_offset.h364 #define MP1_BASE__INST0_SEG1 0 macro
H A Dsienna_cichlid_ip_offset.h705 #define MP1_BASE__INST0_SEG1 0x00DC0000 macro
H A Dbeige_goby_ip_offset.h832 #define MP1_BASE__INST0_SEG1 0x00DC0000 macro
H A Dnavi12_ip_offset.h698 #define MP1_BASE__INST0_SEG1 0x00E80000 macro
H A Dnavi14_ip_offset.h698 #define MP1_BASE__INST0_SEG1 0x00DC0000 macro
H A Ddimgrey_cavefish_ip_offset.h705 #define MP1_BASE__INST0_SEG1 0x00E80000 macro
H A Daldebaran_ip_offset.h1004 #define MP1_BASE__INST0_SEG1 0x00DC0000 macro
H A Dvangogh_ip_offset.h955 #define MP1_BASE__INST0_SEG1 0x0243FC00 macro
H A Darct_ip_offset.h693 #define MP1_BASE__INST0_SEG1 0x00016200 macro

Completed in 355 milliseconds