Searched refs:MP1_BASE__INST0_SEG0 (Results 1 - 16 of 16) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.c38 #define MP1_BASE__INST0_SEG0 0x00016000 macro
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_smu.c38 #define MP1_BASE__INST0_SEG0 0x00016000 macro
/linux-master/drivers/gpu/drm/amd/include/
H A Dcyan_skillfish_ip_offset.h459 #define MP1_BASE__INST0_SEG0 0x00016000 macro
H A Dnavi10_ip_offset.h519 #define MP1_BASE__INST0_SEG0 0x00016000 macro
H A Dvega20_ip_offset.h544 #define MP1_BASE__INST0_SEG0 0x00016000 macro
H A Dyellow_carp_offset.h875 #define MP1_BASE__INST0_SEG0 0x00016000 macro
H A Drenoir_ip_offset.h947 #define MP1_BASE__INST0_SEG0 0x00016200 macro
H A Dvega10_ip_offset.h363 #define MP1_BASE__INST0_SEG0 0x00016200 macro
H A Dsienna_cichlid_ip_offset.h704 #define MP1_BASE__INST0_SEG0 0x00016000 macro
H A Dbeige_goby_ip_offset.h831 #define MP1_BASE__INST0_SEG0 0x00016000 macro
H A Dnavi12_ip_offset.h697 #define MP1_BASE__INST0_SEG0 0x00016200 macro
H A Dnavi14_ip_offset.h697 #define MP1_BASE__INST0_SEG0 0x00016000 macro
H A Ddimgrey_cavefish_ip_offset.h704 #define MP1_BASE__INST0_SEG0 0x00016200 macro
H A Daldebaran_ip_offset.h1003 #define MP1_BASE__INST0_SEG0 0x00016000 macro
H A Dvangogh_ip_offset.h954 #define MP1_BASE__INST0_SEG0 0x00016000 macro
H A Darct_ip_offset.h692 #define MP1_BASE__INST0_SEG0 0x00012020 macro

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